Intel Skylake平台开源HD图形程序员参考手册

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"Intel Open Source HD Graphics Programmer's Reference Manual 13/21 是一份针对2015-2016年基于‘Skylake’平台的Intel Core™、Celeron™和Pentium™处理器中Intel Iris™ Graphics和Intel Iris™ Pro Graphics的程序员指南。这份文档详细介绍了媒体VDBOX相关的技术内容，并在2016年5月发布了1.0版本。" 这篇文档主要涵盖了Intel开源高清显卡编程的相关知识，它对于那些希望深入理解并开发针对Intel HD Graphics、Intel Iris Graphics以及Intel Iris Pro Graphics硬件的软件开发者来说极其宝贵。以下是该参考手册可能包含的一些关键知识点： 1. **Skylake架构**：Skylake是Intel第六代微架构，它在CPU性能、功耗管理以及集成图形处理能力方面有显著提升。文档将详细介绍该架构下GPU的工作原理和优化策略。 2. **GPU编程模型**：手册可能会介绍如何利用OpenCL、OpenGL或DirectX等API来编程，以利用Intel HD Graphics的并行计算能力。这包括数据并行性、任务并行性和流处理概念。 3. **媒体VDBOX**：VDBOX是Intel GPU中用于视频编解码的硬件单元。手册将深入解释如何高效地利用这些硬件加速器进行高清视频编码和解码，以及如何进行硬件加速的图像处理。 4. **图形渲染**：手册会涵盖图形管线的各个阶段，包括顶点处理、光栅化、纹理映射等，并讨论如何优化这些过程以提高渲染效率。 5. **内存管理和带宽优化**：由于GPU处理需要大量数据交换，所以有效的内存管理和带宽优化至关重要。手册可能会指导开发者如何有效地使用显存和系统内存，减少延迟，提高性能。 6. **电源管理**：Skylake平台支持动态电源管理，手册将解释如何在保证性能的同时，实现能效最大化。 7. **错误处理和调试**：为了解决开发过程中可能出现的问题，手册会提供关于错误报告、调试工具和最佳实践的信息。 8. **许可证和免责声明**：文档强调了其内容的创作共享许可条件，同时也指出Intel不提供任何明示或暗示的知识产权许可，且不对产品的销售或使用承担任何责任。这份Intel Open Source HD Graphics Programmer's Reference Manual是开发者深入理解Skylake平台GPU特性和优化代码的关键参考资料，对于那些希望充分利用Intel图形硬件潜力的人来说，是一份不可多得的学习材料。

Doc Ref # IHD-OS-SKL-Vol 8-05.16

MFD Codec-Specific Commands

MFD hardware pipeline supports 3 different codec standards : AVC, VC1 and MPEG2. To make the

interface flexible, each codec is designed with its own set of commands.

There are two categories of commands for each codec format : one set for VLD mode and one set for IT

mode.

MFX State Model

The parallel video engine (PVE) supports two state delivery models: inline state model and indirect state

model. For inline state model, the state commands (*_STATE) can be issued in batch buffers or ring

buffers directly preceding object commands (*_OBJECT). In the indirect state model, the state commands

are not placed in the batch buffers or ring buffers. Instead Indirect State Buffers provide state

information (in the form of the above mentioned state commands) for the MFX pipeline. See

MFX_STATE_POINTER for more details.

VCS (aka BCS) handles the difference of the two state delivery models. Therefore, the MFX pipeline

always sees the state commands in both models. However, MFX hardware supports additional context

save/restore of ‘dynamic states’. Dynamic states are the internal signals that are persistent. This could be

the CABAC context for macroblock encoding.

Doc Ref # IHD-OS-SKL-Vol 8-05.16

MFX State Model

The MFX codec is designed to be a stateless engine, that it does not retain any history of settings (states)

for the encoding/decoding process of a picture. Hence, driver must issue the full set of MFX picture state

command sequence prior to process each new picture. In addition, driver must issue the full set of Slice

state command sequence prior to process a slice.

 In particular, RC6 always happens between frame boundaries. So at the beginning of every frame,

all state information needs to be programmed. There is no state information as part of media

context definition.

MFX Interruptability Model

MFX encoding and the encoding pipeline do not support interruption. All operations are frame based.

Interrupts can only occur between frames; the driver will submit all the states at the beginning of each

frame. Any state kept across frames is in MMIO registers that should be read between frames.

Software submits without any knowledge of where the parser head pointer is located. Also there is a

non-deterministic amount of time for the new context to reach the command streamer. However, the

state model for the MFX engine requires software to know exactly what state the pipeline is in at all

times. This introduces cases where a preemption could occur during or after a state change without

software ever knowing the state saved out to memory on the context switch.

Also, preemption is only allowed during the last macroblock in a row. Hardware cannot always perform a

context switch when the new context is seen by the hardware. To avoid a switch during an invalid

macroblock and to keep the state synchronized with software, there are two commands available that are

used. MI_ARB_ON_OFF disables and enables preemption while MFX_WAIT ensures the context switch, if

needed, preempts during macroblock execution. Below illustrates an example assuming VC1 VLD mode.

Command Ring/Batch

Notes

MI_ARB_ON_OFF = OFF

Disable preemption

Inline or indirect state cmd 1

Inline or indirect state cmd 2

Inline or indirect state cmd 3

XXXX_OBJECT

Slice

MI_ARB_ON_OFF = ON

Enable preemption

MFX_WAIT

Allow preemption to occur while XXXX_OBJECT executes

MI_ARB_ON_OFF = OFF

Since arbitration is off again, state commands are allowed below

Inline or indirect state cmd 4

Inline or indirect state cmd 5

Inline or indirect state cmd 6

XXXX_OBJECT

Slice

MI_ARB_ON_OFF = ON

Enable preemption

MFX_WAIT

Allow preemption to occur while XXXX_OBJECT executes

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Intel Skylake平台开源HD图形程序员参考手册

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