TI-TUSB1004：USB3.2四通道线性重驱动器

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"TI-TUSB1004是TI公司的一款USB3.2 10Gbps四通道自适应线性重驱动器，适用于USB Type-A应用。" TI-TUSB1004是一款针对高数据传输速率需求设计的集成电路，旨在提升USB连接的信号质量和稳定性。该器件支持USB3.2标准的两种速率模式：Gen2（10Gbps）和Gen1（5Gbps），同时兼容USB3.2的低功耗状态，如断开（Disconnect）、U1、U2和U3状态。 1. 功能特性： - **USB3.2 5Gbps及10Gbps支持**：TUSB1004能够处理两种不同的传输速率，以满足不同设备的需求。 - **高级USB电源管理**：在活动状态下，典型功耗为550mW；断开连接时，功耗降至1.7mW；当使能引脚（EN）为低电平时，功耗仅为0.130mW，实现了低功耗设计。 - **16级均衡设置**：最高可达12dB的均衡增益，频率可达5GHz，确保高速信号的准确传输。 - **自适应或固定接收均衡**：可根据面对USB连接器的端口选择自适应或固定的接收均衡策略。 - **线性或有限重驱动选择**：对于面向系统的SSRX1/2发射器端口，可以选择线性或有限重驱动模式，优化信号质量。 - **小于1V的TX-CM和RX-CM**：降低共模电压，提高信号完整性。 - **通过I2C或引脚配置**：用户可以通过I2C接口或引脚设定来调整设备参数。 - **1.8V或3.3V I2C电平选择**：提供两种I2C通信电压等级以适应不同系统需求。 - **单一3.3V电源供电**：简化电源管理，减少外部组件需求。 2. 应用场景： - **笔记本电脑和台式机**：提升内置USB接口的数据传输性能。 - **坞站**：增强坞站与各种设备间的USB连接可靠性。 - **数据存储**：改善硬盘驱动器、固态硬盘等数据存储设备的高速数据传输。 - **外接周边设备和打印机**：保证打印机、扫描仪等USB设备的数据传输速度和稳定性。 TUSB1004是专为应对高速USB数据传输挑战而设计的解决方案，其自适应接收均衡和低功耗特性使得它成为笔记本来、桌面电脑、坞站、数据存储设备和外设的理想选择。通过I2C配置，用户可以灵活调整设备参数以适应各种系统环境，确保最佳的USB连接性能。

5.7 USB Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

USB Gen 2 Differential Receiver (CRX1p/n, CRX2p/n, SSTX1p/n, SSTX2p/n)

(RX-DIFF-PP)

Input differential peak-peak voltage

swing linear dynamic range

AC-coupled differential peak-to-peak

signal measured post CTLE through a

reference channel

1200 mVpp

(RX-DC-CM)

Common-mode voltage bias in the

receiver (DC)

0 V

RX_CM-INST

Max Instantaneous RX DC common

mode voltage change under all

operating conditions (OFF to ON,

Disabled to USB, etc…)

Measured at non-device side of AC

coupling capacitor with 200-kΩ load.

-300 500 mV

(RX-DIFF-DC)

Differential input impedance (DC) Present after a GEN2 device is detected. 72 90 120 Ω

(RX-CM-DC)

Receiver DC common mode

impedance

Present after a GEN2 device is detected. 18 30 Ω

(RX-HIGH-IMP-DC-POS)

Common-mode input impedance with

termination disabled (DC)

Present when no GEN2 device is detected

on transmitter.

Measured over the range of 0 – 500 mV

with respect to GND.

25 kΩ

(SIGNAL-DET-DIFF-PP)

Input differential peak-to-peak signal

detect assert level

At 10 Gbps, no input loss, PRBS7 pattern 75 mV

(RX-IDLE-DET-DIFF-PP)

Input differential peak-to-peak signal

detect de-assert Level

At 10 Gbps, no input loss, PRBS7 pattern 55 mV

(RX-LFPS-DET-DIFF-PP)

Low frequency periodic signaling

(LFPS) detect threshold

Below the minimum is squelched 100 300 mV

(RX-CM-AC-P)

Peak RX AC common-mode voltage Measured at package pin 150 mV

(RX)

RX input capacitance to GND At 5 GHz; 1 pF

L(RX-DIFF)

Differential return Loss

50 MHz – 1.25 GHz at 85 Ω; -22 dB

5 GHz at 85 Ω; -20 dB

L(RX-CM)

Common-mode return loss 50 MHz – 5 GHz at 85 Ω; -12 dB

Q_SSTX15

SSTX1->CTX1 Receiver equalization

at 5 GHz

SSEQ1_SEL = 15; Gain at 5 GHz minus

Gain at 10 MHz;

13.6 dB

Q_RX15

CRX1 -> SSRX1 Receiver

equalization at 5 GHz

CEQ1_SEL = 15; Gain at 5 GHz minus

Gain at 10 MHz;

12.7 dB

AC-USB1

Required external AC capacitor on

SSTX1/2

75 265 nF

AC-USB2

Optional external AC capacitor on

CRX1 and CRX2.

297 363 nF

USB Gen 2 Differential Transmitter (CTX1p/n, CTX2p/n, SSRX1p/n, SSRX2p/n)

TX(DIFF-PP)

Transmitter dynamic differential

voltage swing range.

EQ15; VID = 1Vpp; LINR_L3 1200 mVpp

TX(RCV-DETECT)

Amount of voltage change allowed

during receiver detection

600 mV

TX-CM-INST-ONOFF

Max Instantaneous TX DC common

mode voltage change under operating

condition: OFF to ON, ON to OFF,

during Rx.Detect; Disconnect to U0,

U2/U3 to Disconnect.

Measured single-ended at non-device side

of AC coupling capacitor with 200-kΩ

load.

-500 800 mV

TX(CM-IDLE-DELTA)

Transmitter idle common-mode

voltage change while in U2/U3 and not

actively transmitting LFPS

–300 600 mV

TX(DC-CM)

Common-mode voltage bias in the

transmitter (DC)

0.5 0.76 1 V

TX(CM-AC-PP-ACTIVE)

Tx AC common-mode voltage active

Max mismatch from Txp + Txn for both

time and amplitude

100 mVpp

TX(IDLE-DIFF-AC-PP)

AC electrical idle differential peak-to-

peak output voltage

At package pins 0 10 mV

TX(CM-DC-ACTIVE-

IDLE-DELTA)

Absolute DC common-mode voltage

between U1 and U0

At package pin 200 mV

TX(DIFF)

Differential impedance of the driver 80 90 120 Ω

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5.7 USB Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TX(CM)

Common-mode impedance of the

driver

Measured with respect to AC ground over

0–500 mV

18 30 Ω

SSRX-LIMITED-VODL0

SSRX differential peak-to-peak

voltage when configured for limited

redriver and LINR_L0

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN = 0;

750 mVpp

SSRX-LIMITED-VODL1

SSRX differential peak-to-peak

voltage when configured for limited

redriver and LINR_L1

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN = 0;

900 mVpp

SSRX-LIMITED-VODL2

SSRX differential peak-to-peak

voltage when configured for limited

redriver and LINR_L2

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN = 0;

1000 mVpp

SSRX-LIMITED-VODL3

SSRX differential peak-to-peak

voltage when configured for limited

redriver and LINR_L3

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN = 0;

1100 mVpp

SSRX-DE-RATIO0

SSRX de-emphasis when configured

for limited redriver and de-emphasis

enabled.

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN = 1;

TX_DEEPHASIS = 2'b00;

USB_SSRX_VOD = 2'b00 (LINR_L3);

Refer to Figure 6-7

-1.8 dB

SSRX-DE-RATIO1

SSRX de-emphasis when configured

for limited redriver and de-emphasis

enabled.

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN =

1; TX_DEEPHASIS =

2'b01; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-7

-2.1 dB

SSRX-DE-RATIO2

SSRX de-emphasis when configured

for limited redriver and de-emphasis

enabled.

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN =

1; TX_DEEPHASIS =

2'b10; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-7

-3.2 dB

SSRX-DE-RATIO3

SSRX de-emphasis when configured

for limited redriver and de-emphasis

enabled.

TX_PRESHOOT_EN = 0;

TX_DEEMPHASIS_EN =

1; TX_DEEPHASIS =

2'b11; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-7

-3.8 dB

SSRX-PRESH-RATIO0

SSRX pre-shoot level when configured

for limited redriver and pre-shoot

enabled.

TX_PRESHOOT_EN = 1;

TX_DEEMPHASIS_EN =

0; TX_PRESHOOT =

2'b00; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-6

1.6 dB

SSRX-PRESH-RATIO1

SSRX pre-shoot level when configured

for limited redriver and pre-shoot

enabled.

TX_PRESHOOT_EN = 1;

TX_DEEMPHASIS_EN =

0; TX_PRESHOOT =

2'b01; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-6

2.1 dB

SSRX-PRESH-RATIO2

SSRX pre-shoot level when configured

for limited redriver and pre-shoot

enabled.

TX_PRESHOOT_EN = 1;

TX_DEEMPHASIS_EN =

0; TX_PRESHOOT =

2'b10; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-6

2.5 dB

SSRX-PRESH-RATIO3

SSRX pre-shoot level when configured

for limited redriver and pre-shoot

enabled.

TX_PRESHOOT_EN = 1;

TX_DEEMPHASIS_EN =

0; TX_PRESHOOT =

2'b11; USB_SSRX_VOD = 2'b00

(LINR_L3); Refer to Figure 6-6

3.0 dB

TX(SHORT)

TX short circuit current TX± shorted to GND 60 mA

TX(PARASITIC)

TX input capacitance for return loss At package pins, at 5 GHz 1.25 pF

LTX(DIFF)

Differential return loss 50 MHz – 1.25 GHz at 85 Ω -28 dB

LTX(CM)

Common-mode return loss 50 MHz – 5 GHz at 85 Ω -12 dB

TX-AC(COUPLING)

External required AC coupling

capacitor

75 265 nF

AC Characteristics

Crosstalk_CRXTX

Differential crosstalk between CTX1/2

and CRX1/2 signal pairs

85 Ω; At 5 GHz; SSEQ[1:0] = 0; CEQ[1:0]

= 0;

-40 dB

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5.7 USB Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LF-LINRL0

Low-frequency -1dB compression

point at LINR_L0 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

750 mVpp

HF-LINRL0

High-frequency -1dB compression

point at LINR_L0 setting.

5 GHz clock pattern; VID is 200mV to

1200mV in 10mV steps;

650 mVpp

LF-LINRL1

Low-frequency -1dB compression

point at LINR_L1 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

850 mVpp

HF-LINRL1

High-frequency -1dB compression

point at LINR_L1 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

750 mVpp

LF-LINRL2

Low-frequency -1dB compression

point at LINR_L2 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

950 mVpp

HF-LINRL2

High-frequency -1dB compression

point at LINR_L2 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

850 mVpp

LF-LINRL3

Low-frequency -1dB compression

point at LINR_L3 setting.

20 MHz clock pattern; VID is 200 mV to

1200 mV in 10mV steps;

1050 mVpp

HF-LINRL3

High-frequency -1dB compression

point at LINR_L3 setting.

5 GHz clock pattern; VID is 200 mV to

1200 mV in 10 mV steps;

900 mVpp

Low frequency cutoff 200 mV

< V

< 1200 mV

20 50 kHz

TX_DJ_SSTX2-CTX2

TX output deterministic residual jitter

SSTX2-> CTX2.

Optimal EQ setting; 12-in prechannel

(SDD21 = -11.2 dB); 1.6-in post channel

(SDD21 = -1.8 dB); PRBS7; 10 Gbps

.05 UI

TX_DJ_SSTX1-CTX1

TX output deterministic residual jitter

SSTX1-> CTX1.

Optimal EQ setting; 12-in prechannel

(SDD21 = -11.2 dB); 1.6-in post channel

(SDD21 = -1.8 dB); PRBS7; 10 Gbps

.05 UI

5.8 Timing Requirements

MIN NOM MAX UNIT

USB3.1

IDLEEntry

Delay from U0 to electrical idle Refer to Figure 6-4. 10 ns

IDELExit_U1

U1 exit time: break in electrical idle to the

transmission of LFPS

Refer to Figure 6-4. 1 ns

IDLEExit_U2U3

U2/U3 exit time: break in electrical idle to

transmission of LFPS

Refer to Figure 6-4. 10 µs

RXDET_INTVL

RX detect interval while in Disconnect 12 ms

IDLEExit_DISC

Disconnect Exit Time 10 µs

Exit_SHTDN

Shutdown Exit Time 0.75 ms

AEQ_FULL_DONE

Maximum time to obtain optimum EQ setting

when operating in Full AEQ mode.

400 µs

AEQ_FAST_DONE

Maximum time to determine appropriate EQ

setting when operating in Fast AEQ mode.

60 µs

DIFF_DLY

Differential Propagation Delay Refer to Figure 6-3. 300 ps

, t

Output Rise/Fall time

20%-80% of differential voltage

measured 1.7 inch from the

output pin; Refer to Figure 6-5.

30 ps

RF_MM

Output Rise/Fall time mismatch

20%-80% of differential voltage

measured 1.7 inch from the

output pin

2.6 ps

Power-up

EN_LOW

EN pin held low after supply reaches VCC(min) Refer to Figure 6-1 5 ms

CFG_SU

CFG

(1)

high Refer to Figure 6-1 250 µs

CFG_HD

CFG

(1)

high Refer to Figure 6-1 500 µs

(1) Following pins comprise CFG pins: MODE, CEQ[1:0], SSEQ[1:0], EQCFG, AEQCFG

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