24AA16/24LC16B：IIC与2线串口通讯转换芯片
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"这篇文档介绍了Microchip Technology Inc.的24AA16/24LC16B设备，这是一款16K比特的电可擦除只读存储器（EEPROM），支持IIC（两线串口）通信协议。这款芯片具有低功耗的CMOS技术，适用于各种应用场合，包括工业级和汽车级的温度范围。"
文章内容详细说明了24AA16/24LC16B设备的主要特性与功能：
1. **电源兼容性**：24AA16设备可以在低至1.7V的电压下工作，而24LC16B设备则需要2.5V的电源。这使得它们在不同电源条件下的应用更具灵活性。
2. **低功耗设计**：芯片采用CMOS技术，运行时电流典型值为1mA，待机时电流仅为1μA，这使其在电池供电或对能耗有严格要求的系统中非常适用。
3. **2-Wire Serial Interface (I2C 兼容)**：24XX16*设备通过两线串行接口与主机进行通信，这种接口简化了硬件设计，降低了引脚数量，同时也兼容IIC标准，便于与其他I2C设备集成。
4. **噪声抑制**：Schmitt Trigger输入设计可以有效抑制噪声，提高信号的抗干扰能力。
5. **输出斜率控制**：这一特性有助于消除地线反弹问题，确保信号传输的稳定性。
6. **时钟兼容性**：芯片支持100kHz和400kHz的时钟频率，适应不同速度需求的系统。
7. **快速写入**：页面写入时间最大为5ms，提高了数据写入的效率。
8. **自我定时的擦除/写入周期**：设备内置自我定时的擦除和写入循环，简化了操作流程。
9. **16-Byte Page Write Buffer**：缓冲区允许一次写入最多16字节的数据，优化了批量写入操作。
10. **硬件写保护**：提供硬件级别的写保护，防止意外修改存储数据。
11. **ESD保护**：芯片具有超过4,000V的静电放电保护，增强了其在恶劣环境中的可靠性。
12. **耐用性**：可进行超过1百万次的擦写周期，数据保持时间超过200年，保证了长期的数据稳定性。
13. **封装形式**：该设备提供了多种封装选项，如8引脚PDIP、SOIC、TSSOP、MSOP、DFN、TDFN和SOT-23-5，满足不同应用场景的需求。
14. **温度范围**：针对不同的使用环境，提供两种温度范围版本——工业级(-40°C to +85°C)和汽车级(-40°C to +125°C)。
24AA16/24LC16B设备是适合于需要低功耗、可靠性和高集成度的I2C通信系统的理想选择，特别是在需要大量数据存储和高效能通信的嵌入式系统中。
24AA16/24LC16B
DS21703H-page 6 © 2009 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX16 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur it will replace data in a first-in first-out (FIFO)
fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX16) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX16 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
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