XIO2001：PCIe转PCI桥接器，全面兼容与节能设计

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TI-XIO2001是一款高性能的PCI Express (PCIe) 到PCI桥接器，专为满足现代数据中心和高性能计算环境的需求而设计。该产品具备一系列关键特性： 1. **全速PCIe传输**：XIO2001提供完整的×1 PCIe带宽，确保数据传输的高效性。 2. **标准兼容性**：完全符合PCI Express to PCI/PCI-X Bridge Specification Rev. 1.0规范，以及PCI Express Base Specification Rev. 2.0，支持向下兼容旧版PCI和PCI-X标准。 3. **PCILocal Bus支持**：同时遵循PCILocal Bus Specification Rev. 2.3，使得与传统PCI总线设备的协同工作无缝进行。 4. **高级错误报告**：具备先进的错误报告功能，包括错误校验和报告能力（ECRC），对数据完整性有严格的保护。 5. **电源管理**：支持D1、D2、D3热插拔状态，以及D3冷启动，通过L0s和L1状态实现节能，当PCIe链路空闲时自动进入低功耗模式。 6. **唤醒事件和信标支持**：允许外部设备在适当的时候唤醒桥接器，增强系统灵活性。 7. **错误转发**：能够处理PCIe数据中毒和PCI总线奇偶校验错误，确保数据传输的准确性。 8. **时钟选项**：支持100-MHz差分PCIe通用参考时钟或125-MHz单端参考时钟，甚至提供可选的 Spread Spectrum 时钟技术，提高信号质量和抗干扰能力。 9. **低延迟架构**：采用稳健的管道架构设计，减少交易延迟，提高系统响应速度。 10. **PCI Local Bus性能**：保持66-MHz/32-bit的全速传输，支持六个从属PCI总线主控器，内部配置了可配置的2级优先级调度机制。 11. **外部主控器仲裁**：内置PCIArbitrer支持多达6个外部PCI主设备，确保资源的有效管理和竞争解决。 TI-XIO2001作为一款PCIe到PCI桥接器，集成了高性能、兼容性和低延迟的特点，为数据中心和高性能应用提供了强大的连接解决方案，优化了系统性能并提升了整体稳定性。其广泛的应用场景可能包括服务器平台升级、存储设备扩展以及需要PCIe和PCI设备间高效数据交换的场合。

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6.4 Thermal Information

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PNP

Junction-to-free-air thermal

resistance

Low-K JEDEC test board, 1s (single signal layer), no air

flow

50.8

°C/W

High-K JEDEC test board, 2s2p (double signal layer,

double buried power plane), no air flow

24.9

Junction-to-case thermal resistance Cu cold plate measurement process 18.9 °C/W

Junction-to-board thermal

resistance

EIA/JESD 51-8 14.6 °C/W

Junction-to-top of package EIA/JESD 51-2 0.26 °C/W

Junction-to-board EIA/JESD 51-6 7.93 °C/W

Operating ambient temperature

range

XIO2001PNP 0 70

°C

XIO2001IPNP –40 85

Virtual junction temperature

XIO2001PNP 0 105

°C

XIO2001IPNP –40 105

ZAJ

Junction-to-free-air thermal

resistance

Low-K JEDEC test board, 1s (single signal layer), no air

flow

°C/W

High-K JEDEC test board, 2s2p (double signal layer,

double buried power plane), no air flow

58.8

Junction-to-case thermal resistance Cu cold plate measurement process 19 °C/W

Junction-to-board thermal

resistance

EIA/JESD 51-8 32 °C/W

Junction-to-top of package EIA/JESD 51-2 0.5 °C/W

Junction-to-board EIA/JESD 51-6 30 °C/W

Operating ambient temperature

range

XIO2001ZAJ 0 70

°C

XIO2001IZAJ –40 85

Virtual junction temperature

XIO2001ZAJ 0 105

°C

XIO2001IZAJ –40 105

ZWS

Junction-to-free-air thermal

resistance

High-K JEDEC test board, 2s2p (double signal layer,

double buried power plane), no air flow

36.2

°C/W

Junction-to-case thermal resistance Cu cold plate measurement process 18.3 °C/W

Junction-to-board thermal

resistance

EIA/JESD 51-8

20.3

°C/W

Junction-to-top of package EIA/JESD 51-2 0.4 °C/W

Junction-to-board EIA/JESD 51-6 20.1 °C/W

Operating ambient temperature

range

XIO2001ZWS 0 70

°C

XIO2001IZWS –40 85

Virtual junction temperature

XIO2001ZWS 0 105

°C

XIO2001IZWS –40 105

(1) For more details, refer to TI application note IC Package Thermal Metrics (SPRA953).

6.5 Nominal Power Consumption

DEVICES

POWER STATE

(1)

VOLTS AMPERES WATTS

No downstream PCI devices D0 idle

1.5 0.147 0.221

3.3 0.062 0.205

TOTALS: 0.209 0.426

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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DEVICES POWER STATE

(1)

VOLTS AMPERES WATTS

One downstream PCI device D0 idle

1.5 0.148 0.222

3.3 0.077 0.254

TOTALS: 0.225 0.476

One downstream PCI device D0 active

1.5 0.157 0.236

3.3 0.165 0.545

TOTALS: 0.322 0.780

One downstream (max voltage) D0 active

1.65 0.168 0.277

3.6 0.188 0.677

TOTALS: 0.356 0.954

(1) D0 idle power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is not

actively transferring data.

D0 active power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is acitvely

transferring data (worst case scenario).

6.6 PCI Express Differential Transmitter Output Ranges

PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS

(1)

Unit interval

TXP, TXN 399.88 400 400.12 ps

Each UI is 400 ps ±300 ppm. UI does not account for SSC

dictated variations.

TX-DIFF-PP

Differential peak-to-peak output voltage

TXP, TXN 0.8 1.2 V V

TX-DIFF-PP

= 2*|V

TXP

– V

TXN

TX-DIFF-PP-LOW

Low-power differential peak-to-peak TX

voltage swing

TXP, TXN 0.4 1.2 V V

TX-DIFF-PP

= 2*|V

TXP

– V

TXN

TX-DE-RATIO-3.5dB

TX de-emphasis level ratio

TXP, TXN 3 4 dB

This is the ratio of the V

TX-DIFF-PP

of the second and

following bits after a transition divided by the V

TX-DIFF-PP

the first bit after a transition.

TX-EYE

(2)

(3)

(4)

Minimum TX eye width

TXP, TXN 0.75 UI Does not include SSC or Ref

CLK

jitter. Includes R

at 10

–12

TX-EYE-MEDIAN-to-MAX-JITTER

(2)

Maximum time between the jitter median

and maximum deviation from the median

TXP, TXN 0.125 UI

Measured differentially at zero crossing points after

applying the 2.5 GT/s clock recovery function.

TX-RISE-FALL

(2)

TX output rise/fall time

TXP, TXN 0.125 UI Measured differentially from 20% to 80% of swing.

TX-PLL

(6)

Maximum TX PLL bandwidth

TXP, TXN 22 MHz Second order PLL jitter transfer bounding function.

TX-PLL-LO-3DB

(6)

(7)

Minimum TX PLL bandwidth

TXP, TXN 1.5 MHz Second order PLL jitter transfer bounding function.

TX-DIFF

Tx package plus Si differential return loss

TXP, TXN 10 dB

TX-CM

Tx package plus Si common mode return

loss

TXP, TXN 6 dB Measured over 0.05–1.25 GHz range

TX-DIFF_DC

DC differential TX impedance

TXP, TXN 80 120 Ω Low impedance defined during signaling.

TX-CM-AC-P

(5)

AC common mode voltage

TXP, TXN 20 mV

TX-SHORT

Transmitter short-circuit current limit

TXP, TXN 90 mA

The total current transmitter can supply when shorted to

ground.

TX-DC-CM

Transmitter DC common-mode voltage

TXP, TXN 0 3.6 V

The allowed DC common-mode voltage at the transmitter

pins under any conditions.

TX-CM-DC-ACTIVE-IDLE-DELTA

Absolute delta of DC common mode

voltage during L0 and electrical idle

TXP, TXN 0 100 mV

|VTX-CM-DC – VTX-CM-Idle-DC| ≤ 100 mV

TX-CM-DC

= DC

(avg)

of |V

TXP

+ V

TXN

|/2 [during L0]

TX-CM-Idle-DC

= DC

(avg)

of |V

TXP

+ V

TXN

|/2 [during electrical

idle]

TX-CM-DC-LINE-DELTA

Absolute delta of DC common mode

voltage between P and N

TXP, TXN 0 25 mV

TXP-CM-DC

– V

TXN-CM-DC

| ≤25 mV when

TXP-CM-DC

= DC

(avg)

of |V

TXP

| [during L0]

TXN-CM-DC

= DC

(avg)

of |V

TXN

| [during L0]

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PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS

TX-IDLE-DIFF-AC-p

Electrical idle differential peak output

voltage

TXP, TXN 0 20 mV V

TX-IDLE-DIFFp

= |V

TXP-Idle

– V

TXN-Idle

| ≤ 20 mV

TX-RCV-DETECT

The amount of voltage change allowed

during receiver detection

TXP, TXN 600 mV

The total amount of voltage change that a transmitter can

apply to sense whether a low impedance receiver is

present.

TX-IDLE-MIN

Minimum time spent in electrical idle

TXP, TXN 20 ns Minimum time a transmitter must be in electrical idle.

TX-IDLE-SET-TO-IDLE

Maximum time to transition to a valid

electrical idle after sending an EIOS

TXP, TXN 8 ns

After sending the required number of EIOSs, the

transmitter must meet all electrical idle specifications

within this time. This is measured from the end of the last

EIOS to the transmitter in electrical idle.

TX-IDLE-TO-DIFF-DATA

Maximum time to transition to a valid diff

signaling after leaving electrical idle

TXP, TXN 8 ns

Maximum time to transistion to valid diff signaling after

leaving electrical idle. This is considered a debounce time

to the Tx.

AC coupling capacitor

TXP, TXN 75 200 nF

All transmitters shall be AC coupled. The AC coupling is

required either within the media or within the transmitting

component itself.

(1) SCC permits a 0, –5000 ppm modulation of the clock frequency at a modulation rate not to exceed 33 kHz.

(2) Measurements at 2.5 GT/s require a scope with at least 6.2 GHz bandwidth. 2.5 GT/s may be measured within 200 mils of Tx device's

pins, although deconvolution is recommended.

(3) Transmitter jitter is measured by driving the transmitter under test with a low jitter "ideal" clock and connecting the DUT to a reference

board.

(4) Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW. After the

convolution process has been applied, the center of the resulting eye must be determined and used as a reference point for obtaining

eye voltage and margins.

(5) Measurement is made over at least 10 UI.

(6) The Tx PLL Bandwidth must lie between the min and max ranges given in the above table. PLL peaking must lie below the value listed

above. Note: the PLL B/W extends from zero up to the value(s) specified in the above table.

(7) A single combination of PLL BW and peaking is specified for 2.5 GT/s implemenations.

6.7 PCI Express Differential Receiver Input Ranges

PARAMETER

TERMINALS MIN NOM MAX UNIT COMMENTS

(1)

Unit interval

RXP, RXN 399.88 400.12 ps

Each UI is 400 ps ±300 ppm. UI does not account for

SSC dictated variations.

RX-DIFF-PP-CC

(2)

Differential input peak-to-peak voltage

RXP, RXN 0.175 1.200 V V

RX-DIFFp-p

= 2*|V

RXP

– V

RXN

RX-EYE

(2)

(3)

Minimum receiver eye width

RXP, RXN 0.4 UI

The maximum interconnect media and transmitter jitter

that can be tolerated by the receiver is derived as T

RX-

MAX-JITTER

= 1 – T

RX-EYE

= 0.6 UI

RX-EYE-MEDIAN-to-MAX-JITTER

(2)

(3)

Maximum time between the jitter median

and maximum deviation from the median

RXP, RXN 0.3 UI

Jitter is defined as the measurement variation of the

crossing points (V

RX-DIFFp-p

= 0 V) in relation to

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive UIs of sample data. Jitter is

measured using all edges of the 250 consecutive UIs in

the center of the 3500 UIs used for calculating the TX

UI.

RX-PLL-HI

(6)

Maximum Rx PLL bandwidth

RXP, RXN 22 MHz Second order PLL jitter transfer bounding function.

RX-PLL-LO-3DB

(6)

Minimum Rx PLL for 3 dB peaking

RXP, RXN 1.5 MHz Second order PLL jitter transfer bounding function.

RX-CM-AC-P

(2)

AC peak common mode input voltage

RXP, RXN 150 mV

RX-CM-AC-P

= RMS(|V

RXP

+ V

RXN

|/2 – V

RX-CM-DC

)

RX-CM-DC

= DC

(avg)

of |V

RXP

+ V

RXN

|/2.

RX-DIFF

(4)

Differential return loss

RXP, RXN 10 dB

Measured over 50 MHz to 1.25 GHz with the P and N

lines biased at +300 mV and –300 mV, respectively.

RX-CM

(4)

Common mode return loss

RXP, RXN 6 dB

Measured over 50 MHz to 1.25 GHz with the P and N

lines biased at +300 mV and –300 mV, respectively.

RX-DIFF-DC

(5)

DC differential input impedance

RXP, RXN 80 120 Ω RX dc differential mode impedance

RX-DC

(4)

(5)

DC input impedance

RXP, RXN 40 60 Ω

Required RXP as well as RXN dc impedance (50 Ω

±20% tolerance).

XIO2001

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PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS

RX-HIGH-IMP-DC-POS

(7)

DC input CM input impedance for V > 0

during reset or powerdown

RXP, RXN 50 kΩ

Rx DC CM impedance with the Rx terminations not

powered, measured over the range 0 to 200 mV with

respect to ground.

RX-HIGH-IMP-DC-NEG

(7)

DC input CM input impedance for V > 0

during reset or powerdown

RXP, RXN 1 kΩ

Rx DC CM impedance with the Rx terminations not

powered, measured over the range 0 to 200 mV with

respect to ground.

RX-IDLE-DET-DIFFp-p

Electrical idle detect threshold

RXP, RXN 65 175 mV

RX-IDLE-DET-DIFFp-p

= 2*|V

RXP

– V

RXN

| measured at the

receiver package terminals

RX-IDLE-DET-DIFF-ENTER-TIME

Unexpected electrical idle enter detect

threshold integration time

RXP, RXN 10 ms

An unexpected electrical idle (V

RX-DIFFp-p

< V

RX-IDLE-

DET-DIFFp-p

) must be recognized no longer than T

RX-IDLE-

DET-DIFF-ENTER-TIME

to signal an unexpected idle

condition.

(1) No test load is necessarily associated with this value.

(2) Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when

taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, then the TX UI recovered from

3500 consecutive UIs is used as a reference for the eye diagram.

(3) A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect

collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the

median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX

UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of

jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived

from the same reference clock, then the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye

diagram.

(4) The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and

the N line biased to .300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range

of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements for is 50 . to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50-. probes). The

series capacitors CTX is optional for the return loss measurement.

(5) Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect

state (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured

lane of a port.

(6) A single PLL bandwidth and peaking value of 1.5 to 22 MHz and 3 dB are defined.

(7) Z

RX-HIGH-IMP-DC-NEG

and Z

RX-HIGH-IMP-DC-POS

are defined respectively for negative and postive voltages at the input of the receiver.

6.8 PCI Express Differential Reference Clock Input Ranges

(1)

PARAMETER

TERMINALS MIN NOM MAX UNIT COMMENTS

IN-DIFF

Differential input frequency

REFCLK+

REFCLK–

100 MHz

The input frequency is 100 MHz + 300 ppm and –2800

ppm including SSC-dictated variations.

IN-SE

Single-ended input frequency

REFCLK+

125 MHz

The input frequency is 125 MHz + 300 ppm and –300

ppm.

RX-DIFFp-p

Differential input peak-to-

peak voltage

REFCLK+

REFCLK– 0.175 1.2 V V

RX-DIFFp-p

= 2*|V

REFCLK+

– V

REFCLK-

IH-SE

REFCLK+

0.7 V

DDA_33

Single-ended, reference clock mode high-level input

voltage

IL-SE

REFCLK+

0 0.3 V

DDA_33

Single-ended, reference clock mode low-level input

voltage

RX-CM-ACp

AC peak common mode input

voltage

REFCLK+

REFCLK– 140 mV

RX-CM-ACp

= RMS(|V

REFCLK+

+ V

REFCLK-

|/2 V

RX-CM-DC

)

RX-CM-DC

= DC

(avg)

REFCLK+

+ V

REFCLK-

|/2

Duty cycle

REFCLK+

REFCLK–

40% 60%

Differential and single-ended waveform input duty

cycle

C-DC

Clock source DC impedance

REFCLK+

REFCLK–

40 60 Ω REFCLK± dc differential mode impedance

RX-DC

DC input impedance

REFCLK+

REFCLK–

20 kΩ REFCLK+ dc single-ended mode impedance

(1) The XIO2001 is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. Any

usage of the XIO2001 in a system configuration that does not conform to the defined system jitter models requires the system designer

to validate the system jitter budgets.

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6.9 PCI Bus Electrical Characteristics

over recommended operating conditions

(3)

PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT

High-level input voltage

(1)

PCIR = 3.3 V 0.5 × V

DD_33

PCIR + 0.5

PCIR = 5 V 2.0 PCIR + 0.5

Low-level input voltage

(1)

PCIR = 3.3 V –0.5 0.3 × V

DD_33

PCIR = 5 V –0.5 0.8

Input voltage 0 PCIR V

Output voltage

(2)

0 V

DD_33

Input transition time (t

rise

and t

fall

) 1 4 ns

High-level output voltage

PCIR = 3.3 V I

= –500 μA 0.9 × V

DD_33

PCIR = 5 V I

= –2 mA 2.4

Low-level output voltage

PCIR = 3.3 V I

= 1500 μA 0.1 × V

DD_33

PCIR = 5 V I

= 6 mA 0.55

High-impedance, output current

(2)

PCIR = 3.3 V ±10

μA

PCIR = 5 V ±70

Input current

PCIR = 3.3 V ±10

μA

PCIR = 5 V ±70

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) This table applies to CLK, CLKOUT6:0, AD31:0,

C/BE[3:0], DEVSEL, FRAME, GNT5:0, INTD:A, IRDY, PAR, PERR, REQ5:0, PRST,

SERR, STOP, TRDY, SERIRQ, M66EN, and LOCK terminals.

6.10 3.3-V I/O Electrical Characteristics

over recommended operating conditions

(5)

PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT

High-level input voltage

(1)

DD_33

0.7 V

DD_33

VIL Low-level input voltage

(1)

DD_33

0 0.3 V

DD_33

Input voltage 0 V

DD_33

Output voltage

(2)

0 V

DD_33

Input transition time (t

rise

and t

fall

) 0 25 ns

hys

Input hysteresis

(4)

0.13 V

DD_33

High-level output voltage V

DD_33

= –4 mA 0.8 V

DD_33

Low-level output voltage V

DD_33

= 4 mA 0.22 V

DD_33

High-impedance, output current

(2)

DD_33

= 0 to V

DD_33

±20 μA

OZP

High-impedance, output current with internal

pullup or pulldown resistor

(5)

DD_33

= 0 to V

DD_33

±100 μA

Input current

(3)

DD_33

= 0 to V

DD_33

±1 μA

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) Applies to external input buffers.

(4) Applies to

PERST, GRST, and PME.

(5) Applies to GRST (pullup), EXT_ARB_EN (pulldown), CLKRUN_EN (pulldown), and most GPIO (pullup).

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