S5P4418应用处理器用户手册

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"SEC_Users_Manual_S5P4418_Users_Manual_Preliminary" 是一份关于S5P4418应用处理器的初步用户手册，版本为0.10，由Samsung Electronics Co., Ltd.在2014年10月发布。这份文档可能是针对开发人员和系统集成者的参考资料，旨在介绍该处理器的关键特性和使用方法。 S5P4418是Samsung公司的一款应用处理器，其 datasheet 提供了详细的硬件规格和技术参数。在 datasheet 中，通常会包含以下关键信息： 1. 产品概述：S5P4418的架构、性能指标，如处理器核心数量、时钟速度、内存接口类型和容量等。 2. 功能特性：处理器支持的多媒体功能，如图像处理单元（GPU）、视频编码/解码能力、显示接口（如LCD和HDMI）以及其他外设接口（如USB、Ethernet、Wi-Fi和蓝牙）。 3. 电气特性：电源电压要求、功耗数据、引脚配置和信号电平标准。 4. 封装信息：处理器的物理尺寸、引脚排列和封装类型，这对于硬件设计者进行PCB布局至关重要。 5. 开发工具和支持：可能包括SDK（软件开发套件）、调试工具、驱动程序库和示例代码，这些对于开发者快速上手和优化应用程序非常有帮助。 6. 兼容性和认证：处理器可能需要满足的行业标准和认证，如EMC、安规等。 7. 注意事项和免责声明：Samsung在手册中声明保留随时更改信息的权利，且不对因使用手册信息导致的错误、遗漏或后果承担责任。这意味着用户在设计基于S5P4418的产品时，需要密切关注最新的技术更新和文档修订。 8. 知识产权：手册明确指出，它本身并不授予任何关于Samsung或第三方产品的知识产权许可，用户需要遵守所有相关的知识产权法律。 9. 保修和责任：Samsung不保证其产品适用于特定用途，也不承担因产品应用或使用而产生的任何直接或间接责任。这份用户手册对于理解S5P4418的应用场景、设计限制以及系统集成策略具有重要价值。开发者和工程师需要仔细阅读并遵循手册中的指导，确保他们的产品设计符合Samsung的规格要求，并能有效利用S5P4418的性能优势。同时，他们还需要关注Samsung可能发布的任何更新，以确保信息的准确性和时效性。

Samsung Confidential

38.3.1 Block Diagram of MIPI DSI System .............................................................................................. 38-3

38.3.2 Interfaces and Protocol ................................................................................................................. 38-6

38.3.3 Configuration .............................................................................................................................. 38-12

38.3.4 PLL ............................................................................................................................................. 38-12

38.3.5 Buffer .......................................................................................................................................... 38-12

38.4 Register Description ........................................................................................................................... 38-13

38.4.1 Register Map Summary .............................................................................................................. 38-13

38.5 CSIS ................................................................................................................................................... 38-41

38.5.1 Interfaces and Protocol ............................................................................................................... 38-41

38.5.2 Configuration .............................................................................................................................. 38-46

38.5.3 Interrupt ...................................................................................................................................... 38-46

38.5.4 Clock Specification ..................................................................................................................... 38-47

38.5.5 Register Description ................................................................................................................... 38-48

38.6 D-PHY ................................................................................................................................................ 38-60

38.6.1 Architecture ................................................................................................................................. 38-60

39 VIDEO INPUT PROCESSOR (VIP)............................................................ 39-1

39.1 Overview .............................................................................................................................................. 39-1

39.2 Features ............................................................................................................................................... 39-1

39.3 VIP Interconnection .............................................................................................................................. 39-2

39.3.1 Block Diagram .............................................................................................................................. 39-2

39.3.2 Clock Generation .......................................................................................................................... 39-2

39.4 Video Input Port ................................................................................................................................... 39-3

39.4.1 Block Diagram .............................................................................................................................. 39-3

39.4.2 Sync Generation ........................................................................................................................... 39-4

39.4.3 External Data Valid and Field ....................................................................................................... 39-9

39.4.4 Data Order .................................................................................................................................. 39-10

39.4.5 Status .......................................................................................................................................... 39-11

39.4.6 FIFO Controls ............................................................................................................................. 39-11

39.4.7 Recommend Setting for Video Input Port ................................................................................... 39-12

39.5 Clipper & Decimator ........................................................................................................................... 39-13

39.5.1 Clipping & Scale-down ............................................................................................................... 39-13

39.5.2 Output Data Format .................................................................................................................... 39-14

39.5.3 Interlace Scan Mode ................................................................................................................... 39-16

39.5.4 Pixels Alignment ......................................................................................................................... 39-16

39.6 Interrupt Generation ........................................................................................................................... 39-17

39.7 Register Description ........................................................................................................................... 39-18

39.7.1 Register Map Summary .............................................................................................................. 39-18

40 MULTI-FORMAT VIDEO CODEC .............................................................. 40-1

40.1 Overview .............................................................................................................................................. 40-1

40.2 Functional Description ......................................................................................................................... 40-2

40.2.1 List of Video CODECs .................................................................................................................. 40-2

40.2.2 Supported Video Encoding Tools ................................................................................................. 40-3

40.2.3 Supported Video Decoding Tools ................................................................................................. 40-5

40.2.4 Supported JPEG Tools ................................................................................................................. 40-7

40.2.5 Non-codec related features .......................................................................................................... 40-7

41 3D GRAPHIC ENGINE .............................................................................. 41-1

41.1 Overview .............................................................................................................................................. 41-1

41.2 Features ............................................................................................................................................... 41-2

cn / Splendid_wu at 2014.10.27

SAMSUNG Confidential

Samsung Confidential

41.2.1 Pixel Processor Features ............................................................................................................. 41-2

41.2.2 Geometry Processor Features ..................................................................................................... 41-3

41.2.3 Level 2 Cache Controller Features ............................................................................................... 41-3

41.2.4 MMU ............................................................................................................................................. 41-3

41.2.5 PMU .............................................................................................................................................. 41-3

41.3 Operation ............................................................................................................................................. 41-4

41.3.1 Clock ............................................................................................................................................. 41-4

41.3.2 Reset ............................................................................................................................................ 41-4

41.3.3 Interrupt ........................................................................................................................................ 41-4

42 CRYPTO ENGINE ..................................................................................... 42-1

42.1 Overview .............................................................................................................................................. 42-1

42.2 Features ............................................................................................................................................... 42-1

42.3 Block Diagram ...................................................................................................................................... 42-2

42.4 Functional Description ......................................................................................................................... 42-4

42.4.1 Polling Mode ................................................................................................................................. 42-4

42.4.2 Mode ............................................................................................................................................. 42-4

42.5 Register Description ............................................................................................................................. 42-5

42.5.1 Register Map Summary ................................................................................................................ 42-5

43 ELECTRICAL CHARACTERISTICS .......................................................... 43-1

43.1 Absolute Maximum Ratings ................................................................................................................. 43-1

43.2 Recommended Operating Conditions .................................................................................................. 43-2

43.3 D.C. Electrical Characteristics ............................................................................................................. 43-4

cn / Splendid_wu at 2014.10.27

SAMSUNG Confidential

Samsung Confidential

List of Figures

Figure Title Page

Number Number

Figure 1-1 Block Diagram ................................................................................................................................... 1-3

Figure 2-1 Mechanical Dimension - Bottom View .............................................................................................. 2-1

Figure 2-2 Mechanical Dimension - Top, Side View .......................................................................................... 2-2

Figure 2-3 Mechanical Dimension - Dimension Value ....................................................................................... 2-2

Figure 2-4 FCBGA Ball Map (Top View) ............................................................................................................ 2-3

Figure 2-5 FCBGA Ball Map (Top View) - Upper Left Side ................................................................................ 2-4

Figure 2-6 FCBGA Ball Map (Top View) - Upper Right Side ............................................................................. 2-5

Figure 2-7 FCBGA Ball Map (Top View) - Lower Left Side ................................................................................ 2-6

Figure 2-8 FCBGA Ball Map (Top View) - Lower Right Side ............................................................................. 2-7

Figure 3-1 External Static Memory Boot ............................................................................................................ 3-6

Figure 3-2 USBBOOT Operation ....................................................................................................................... 3-8

Figure 3-3 SDHCBOOT Operation ................................................................................................................... 3-11

Figure 3-4 eMMC Boot ..................................................................................................................................... 3-12

Figure 3-5 NANDBOOTEC Operation .............................................................................................................. 3-13

Figure 4-1 Block Diagram ................................................................................................................................... 4-2

Figure 4-2 Block Diagram of PLL ....................................................................................................................... 4-3

Figure 4-3 CPU Clock ...................................................................................................................................... 4-11

Figure 4-4 System BUS Clock.......................................................................................................................... 4-12

Figure 4-5 Memory BUS Clock......................................................................................................................... 4-13

Figure 4-6 System BUS Clock.......................................................................................................................... 4-14

Figure 4-7 System BUS Clock.......................................................................................................................... 4-14

Figure 4-8 Power Management Sequence ...................................................................................................... 4-16

Figure 4-9 Power Down Mode Sequence ........................................................................................................ 4-19

Figure 4-10 Wake Up Block Diagram ............................................................................................................... 4-20

Figure 4-11 Power-On Reset Sequence .......................................................................................................... 4-21

Figure 4-12 Power On Sequence for Wakeup ................................................................................................. 4-22

Figure 4-13 Power Off Sequence ..................................................................................................................... 4-23

Figure 4-14 Example Implementation of ProgQoS Control Registers for 2×1 Interconnect ............................ 4-25

Figure 4-15 Example Operation of RR Arbitration Scheme ............................................................................. 4-27

Figure 5-1 Interconnection Example of Clock Generator ................................................................................... 5-1

Figure 5-2 Block Diagram of Clock Generator Level 0 ...................................................................................... 5-2

Figure 5-3 Block Diagram of Clock Generator Level 1 ...................................................................................... 5-7

Figure 5-4 Block Diagram of Clock Generator Level 2 .................................................................................... 5-18

Figure 6-1 System L2 Cache Block Diagram ..................................................................................................... 6-3

Figure 7-1 Secure JTAG Block Diagram ............................................................................................................ 7-2

Figure 8-1 DMAC Block Diagram ....................................................................................................................... 8-3

Figure 8-2 LLI Example .................................................................................................................................... 8-15

Figure 9-1 Interrupt Request Logic in 1 Channel ............................................................................................... 9-2

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SAMSUNG Confidential

Samsung Confidential

Figure 9-2 FIQ Interrupt Logic in 1 Channel ....................................................................................................... 9-2

Figure 10-1 Watchdog Timer Block Diagram ................................................................................................... 10-2

Figure 11-1 RTC Block Diagram ...................................................................................................................... 11-2

Figure 12-1 Power Switch Control Sequence .................................................................................................. 12-7

Figure 13-1 Sense Mode Timing ...................................................................................................................... 13-3

Figure 13-2 Scan-Latch Mode Timing .............................................................................................................. 13-4

Figure 13-3 Fuse Programming Operation Using Single Macro ...................................................................... 13-5

Figure 13-4 Fuse Programming Operation Using Single Macro ...................................................................... 13-5

Figure 14-1 Memory Controller Block Diagram ................................................................................................ 14-2

Figure 14-2 Memory Map ................................................................................................................................. 14-5

Figure 14-3 Linear Address Mapping ............................................................................................................... 14-6

Figure 14-4 Linear Address Mapping ............................................................................................................... 14-6

Figure 14-5 Static Memory Map Shadow ....................................................................................................... 14-23

Figure 14-6 16-bit Data Bus width SDRAM Interface .................................................................................... 14-24

Figure 14-7 16-bit Data Bus width SDRAM Interface .................................................................................... 14-25

Figure 15-1 GPIO Block Diagram .................................................................................................................... 15-2

Figure 16-1 Block Diagram of the Ethernet MAC ............................................................................................. 16-3

Figure 16-2 RGMII Interface between MAC and Gigabit Ethernet PHY .......................................................... 16-4

Figure 17-1 Block Diagram of Mobile Storage Host ......................................................................................... 17-2

Figure 17-2 Block Diagram of Mobile Storage Host ......................................................................................... 17-3

Figure 18-1 PPM Block Diagram ...................................................................................................................... 18-1

Figure 18-2 IR Remote Example Protocol ....................................................................................................... 18-2

Figure 18-3 PPM Timing .................................................................................................................................. 18-3

Figure 18-4 IR Remote Receiver Flowchart ..................................................................................................... 18-4

Figure 19-1 Simple Example of PWM Cycle .................................................................................................... 19-1

Figure 19-2 PWMTIMER Block Diagram ......................................................................................................... 19-4

Figure 19-3 PWMTIMER Clock Tree Diagram ................................................................................................. 19-5

Figure 19-4 PWMTIMER Detailed Clock Tree Diagram .................................................................................. 19-6

Figure 19-5 Timer Operations .......................................................................................................................... 19-7

Figure 19-6 Example of Double Buffering Feature .......................................................................................... 19-8

Figure 19-7 Example of Timer Operation ......................................................................................................... 19-9

Figure 19-8 Example of PWM ........................................................................................................................ 19-10

Figure 19-9 Inverter On/Off ............................................................................................................................ 19-11

Figure 19-10 The Waveform when a Dead Zone Feature is Enabled ........................................................... 19-12

Figure 20-1 ADC Block Diagram ...................................................................................................................... 20-2

Figure 20-2 Main Waveform ............................................................................................................................. 20-4

Figure 20-3 ADC Sequence Flowchart ............................................................................................................ 20-6

Figure 21-1 Connection of Devices to the I2C-Bus .......................................................................................... 21-3

Figure 21-2 Bi-Direction PAD Structure of the I2C-Bus ................................................................................... 21-3

Figure 21-3 Start/Stop Condition of I2C-Bus.................................................................................................... 21-4

Figure 21-4 I2C-Bus Data Format .................................................................................................................... 21-5

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SAMSUNG Confidential

Samsung Confidential

Figure 21-5 Data Transfer on the I2C-Bus ....................................................................................................... 21-6

Figure 21-6 Arbitration Procedure between Two Masters ............................................................................... 21-7

Figure 21-7 Clock Synchronization .................................................................................................................. 21-8

Figure 21-8 Acknowledge on the I2C-Bus ....................................................................................................... 21-9

Figure 21-9 Timing on the SCL and SDA ....................................................................................................... 21-11

Figure 21-10 Functional Block Diagram of I2C-Bus ....................................................................................... 21-12

Figure 21-11 Master Transmitter Mode Operation ......................................................................................... 21-13

Figure 21-12 Master Receiver Mode Operation ............................................................................................. 21-14

Figure 21-13 Slave Transmitter Mode Operation ........................................................................................... 21-15

Figure 21-14 Slave Receiver Mode Operation ............................................................................................... 21-16

Figure 21-15 Linked Layer of the I2C-Bus ..................................................................................................... 21-17

Figure 21-16 Delays between the I2C-Bus Commands ................................................................................. 21-17

Figure 22-1 SPI/SSP Block Diagram ............................................................................................................... 22-2

Figure 22-2 Texas Instruments Synchronous Serial Frame Format (Single Transfer) .................................... 22-7

Figure 22-3 TI Synchronous Serial Frame Format (Continuous Transfer) ...................................................... 22-8

Figure 22-4 Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 ............................... 22-10

Figure 22-5 Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0 ....................... 22-10

Figure 22-6 Motorola SPI Frame Format with SPO = 0 and SPH = 1 ........................................................... 22-12

Figure 22-7 Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 ............................... 22-13

Figure 22-8 Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 ....................... 22-13

Figure 22-9 Motorola SPI Frame Format with SPO = 1 and SPH = 1 ........................................................... 22-15

Figure 22-10 Microwire frame format (single transfer) ................................................................................... 22-16

Figure 22-11 Microwire Frame Format (Continuous Transfers) ..................................................................... 22-17

Figure 22-12 Microwire Frame Format, SSPFSSIN Input Setup and Hold Requirements ............................ 22-17

Figure 23-1 Basic Transfer Timing Diagram .................................................................................................... 23-2

Figure 23-2 MPEG TS Timing at Serial Mode.................................................................................................. 23-2

Figure 23-3 Capture I/F PID Structure ........................................................................................................... 23-15

Figure 23-4 Basic AES/CSA PID Structure .................................................................................................... 23-15

Figure 24-1 UART Block Diagram .................................................................................................................... 24-4

Figure 24-2 IrDA SIR RNDEC Block Diagram ................................................................................................. 24-7

Figure 24-3 Baud rate divisor ......................................................................................................................... 24-10

Figure 24-4 UART Character Frame .............................................................................................................. 24-14

Figure 24-5 IrDA Data Modulation (3/16) ....................................................................................................... 24-14

Figure 24-6 DMA Transfer Waveforms .......................................................................................................... 24-17

Figure 24-7 Smart Card Adepter Interface ..................................................................................................... 24-21

Figure 25-1 USB 2.0 OTG Block Diagram ....................................................................................................... 25-2

Figure 25-2 Charge Pump Connection ............................................................................................................ 25-6

Figure 26-1 USB2.0 HOST Block Diagram ...................................................................................................... 26-2

Figure 27-1 Block Diagram of the I2S Controller ............................................................................................. 27-2

Figure 27-2 Basic Clock Tree ........................................................................................................................... 27-4

Figure 27-3 I2S Audio Serial Data Formats ..................................................................................................... 27-5

Figure 27-4 TX FIFO Structure for BLC = 00 or BLC = 01 ............................................................................... 27-8

Figure 27-5 TX FIFO Structure for BLC = 10 (24 bits/channel) ....................................................................... 27-9

Figure 27-6 RX FIFO Structure for BLC = 00 or BLC = 01 ............................................................................ 27-11

Figure 27-7 RX FIFO Structure for BLC = 10 (24 bits/channel) ..................................................................... 27-12

Figure 28-1 AC97 Block Diagram .................................................................................................................... 28-2

cn / Splendid_wu at 2014.10.27

SAMSUNG Confidential

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