DS90UB954-Q1：4.16Gbps FPD-LinkIII解串器集线器

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DS90UB954-Q1是一款专为汽车应用设计的高性能双路4.16Gbps FPD-Link III解串器集线器，它符合AEC-Q100标准，适用于2MP/60fps摄像头和雷达系统。该设备的特点包括： 1. **温度适应性**：在-40℃至+105℃的宽温范围内，满足严苛的汽车环境要求，达到AEC-Q100标准2级。 2. **功能集成**：集成了双路FPD-Link III解串器，可同时处理一个或两个有源传感器的数据，支持PoC（功率-over-coaxial）供电方式。 3. **通信协议兼容性**：遵循MIPID PHY版本1.2和CSI-2版本1.3规范，提供CSI-2输出接口，支持1到4个数据通道，数据速率可扩展至400Mbps到1.6Gbps，且支持可编程数据类型和四个虚拟通道。 4. **错误检测与纠正**：内置ECC (错误校验码) 和 CRC (循环冗余校验) 功能，确保数据传输的准确性。 5. **低延迟**：优化的数据和控制路径设计，有助于实现高效的数据传输，降低延迟。 6. **电缆连接灵活性**：支持单端同轴电缆或屏蔽双绞线(STP)连接，适用于多种物理介质。 7. **I2C接口增强**：提供快速模式，最高支持1Mbps的数据传输，便于摄像头同步和系统诊断。 8. **GPIO控制**：具有灵活的通用输入/输出端口，用于摄像头同步和设备控制，提高了系统的灵活性。 9. **与其他产品兼容**：DS90UB954-Q1与DS90UB935-Q1和DS90UB953-Q1等器件配合使用，构建完整的解决方案。最后，值得注意的是，虽然文档提供了中文版本信息，但用户在进行实际设计时应优先参考英文官方网站www.ti.com上的最新官方数据，因为其内容是最新的，并且TI公司对其准确性负责。在设计过程中，务必确保使用的是最新、最准确的产品规格。

DS90UB954-Q1

ZHCSGT3B –AUGUST 2017–REVISED DECEMBER 2018

www.ti.com.cn

AC Electrical Characteristics CSI-2 (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS

PIN OR

FREQUEN

MIN TYP MAX UNIT

RHS

FHS

20% to 80% rise and fall HS

HS bit rates ≤ 1 Gbps (UI ≥ 1 ns)

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

0.3 UI

HS bit rates > 1 Gbps (UI 0.35 UI

Applicable for all HS bit rates.

However, to avoid excessive

radiation, bit rates ≤ 1 Gbps (UI ≥

1 ns), should not use values

below 150 ps

100 ps

Applicable for all HS bit rates

when supporting > 1.5 Gbps

0.4 UI

Applicable for all HS bit rates

when supporting > 1.5 Gbps.

However, to avoid excessive

radiation, bit rates ≤ 1.5 Gbps

should not use values below 100

ps and bit rates ≤ 1 Gbps should

not use values below 150 ps.

50 ps

SDD

TX differential return loss

LPMAX

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

–18 dB

HSData

rates < 1.5

Gbps

–9 dB

HSData

rates > 1.5

Gbps

-4.5 dB

MAX

HSData

rates < 1.5

Gbps

–-3 dB

HSData rates

> 1.5 Gbps

–-2.5 dB

SCC

TX common mode return loss

LPMAX

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

–20 dB

–15 dB

MAX

–9 dB

LPTX DRIVER

AC SPECIFICATIONS

RLP

Rise time LP 15% to 85% rise time CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

25 ns

FLP

Fall time LP 15% to 85% fall time 25 ns

REOT

Rise time post-EoT 30%-85% rise time 35 ns

PULSE-TX

Pulse width of the LP exclusive-

OR clock

First LP exclusive-OR clock pulse

after Stop state or last pulse

before Stop state

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

40 ns

All other pulses 20 ns

LP-PER-TX

Pulse width of the LP exclusive-

OR clock

90 ns

DS90UB954-Q1

ZHCSGT3B –AUGUST 2017–REVISED DECEMBER 2018

www.ti.com.cn

AC Electrical Characteristics CSI-2 (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS

PIN OR

FREQUEN

MIN TYP MAX UNIT

CLK-MISS

Timeout for receiver to detect

absence of clock transitions and

disable the clock lane HS-RX

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

60 ns

CLK-POST

HS exit

60 +

52×UI

CLK-PRE

Time HS clock shall be driver

prior to any associated data lane

beginning the transition from LP

to HS mode

8 UI

CLK-

PREPARE

Clock lane HS entry 38 95 ns

CLK-SETTLE

Time interval during which the

HS receiver shall ignore any

clock lane HS transitions

95 300 ns

CLK-TERM-EN

Time-out at clock lane display

module to enable HS termination

Time for

Dn to

reach

VTERM-

38 ns

CLK-TRAIL

Time that the transmitter drives

the HS-0 state after the last

payload clock bit of a HS

transmission burst

60 ns

CLK-

PREPARE

CLK-ZERO

TCLK-PREPARE + time that the

transmitter drives the HS-0 state

prior to starting the clock

300 ns

D-TERM-EN

Time for the data lane receiver to

enable the HS line termination

CSI_D0P/N,

CSI_D1P/N,

CSI_D2P/N,

CSI_D3P/N,

CSI_CLK0P

/N,

CSI_CLK1P

Time for

Dn to

reach

TERM-EN

35 +

4×UI

EOT

Transmitted time interval from the

start of tHS-TRAIL to the start of

the LP-11 state following a HS

burst

105 +

12×UI

HS-EXIT

Time that the transmitter drives

LP-11 following a HS burst

100 ns

HS-PREPARE

Data lane HS entry

40 +

4×UI

85 +

6×UI

PREPARE

+ t

HS-ZERO

HS-PREPARE

+ time that the

transmitter drives the HS-0 state

prior to transmitting the Sync

sequence

145 +

10×UI

HS-SETTLE

Time interval during which the

HS receiver shall ignore any data

lane HS transitions, starting from

the beginning of tHS-SETTLE

85 +

6×UI

145 +

10×UI

HS-SKIP

Time interval during which the

HS-RX should ignore any

transitions on the data lane,

following a HS burst. The end

point of the interval is defined as

the beginning of the LP-11 state

following the HS burst.

55 +

4×UI

HS-TRAIL

Data lane HS exit

60 +

4×UI

LPX

Transmitted length of LP state 50 ns

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