低偏移动态比较器：输入偏置校正技术

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"A low-offset dynamic comparator with input offset-cancellation" 这篇研究论文介绍了一种低偏置动态比较器，该比较器采用了输入偏置取消技术，旨在解决动态比较器中的偏置问题。动态比较器的主要偏置误差源来自其动态前置放大器。文中提出的创新技术在动态前置放大器和输入串联电容器的帮助下实现输入偏置取消，而且无需静态电流。这种方法能够抵消由阈值电压不匹配和尺寸因子不匹配造成的偏置。论文中提到的原型比较器是采用65纳米CMOS工艺实现的，面积仅为127μm²。仿真结果显示，在1-σ（标准差）下，该设计实现了1.16毫伏的偏置，而没有采用偏置取消技术的同类比较器在相同条件下偏置达到了8.91毫伏。经过后布局仿真，1-σ下的偏置仅略微增加到1.56毫伏，表明该设计具有良好的偏置稳定性。功耗方面，尽管文章没有给出具体数值，但提到了该设计在保持较低偏置误差的同时，也考虑了功耗效率，这在高速、低功耗的集成电路设计中尤为重要。输入偏置取消技术的应用降低了对高精度制造工艺的依赖，从而降低了整体设计的复杂性和成本。此外，这种动态比较器可能适用于各种信号处理应用，如ADC（模拟数字转换器）和数据采样系统，其中对比较器的偏置误差有严格要求。通过输入偏置取消，可以提高系统的整体精度和信噪比，进一步优化系统性能。这篇论文提出的技术为设计低偏置误差的动态比较器提供了一个新的解决方案，对于推动高性能、低功耗的集成电路发展具有重要意义。通过减少偏置误差，它为实现更高效、更可靠的电子设备提供了理论和技术支持。

A Low-Offset Dynamic Comparator with Input Offset-Cancellation

Ruihan Pei

, Jia Liu

, Xian Tang

, Fule Li

* and Zhihua Wang

Institute of Microelectronics, Tsinghua University, Beijing 100084, China

Graduate School at Shenzhen, Tsinghua University, Shenzhen, China

*Email: lifule@mail.tsinghua.edu.cn

Abstract

This paper presents a low-offset dynamic comparator

using an input offset-cancellation technique. The offset of

a dynamic comparator is mainly determined by the

dynamic preamplifier. The proposed technique achieves

input offset-cancellation under the assistance of the

dynamic preamplifier and input-series capacitors, without

quiescent current. The offset resulting from both threshold

voltage mismatch and sizing factor mismatch can be

cancelled. A prototype comparator is implemented by 65-

nm CMOS technology with an area of 127μm

. The

simulation results show it achieves 1.16-mV offset at 1-

sigma(σ), while its counterpart without offset-

cancellation achieves 8.91-mV offset at 1-sigma(σ). After

post-layout simulation, the offset at 1-sigma(σ) only

slightly increases to 1.56-mV. The power dissipation is

135-μW from a 1.2V supply, at 500MHz operating.

1. Introduction

With the data processing speed of modern electronic

system rising, high-performance analog-to-digital

converters (ADC) have become an inevitable trend. As an

important component in ADCs, the comparator and its

performance optimization are very vital.

Because of its low power consumption, high speed,

high input impedance and good compatibility with deep

sub-micron processes, the dynamic comparator with a

dynamic preamplifier followed by a regenerative latch is

very attractive in high speed and resolution applications.

It can amplify a small input voltage difference to a large

voltage to overcome the backend latch’s offset and

prevents the kickback noise [1]. Fig. 1 redraws one

conventional double–tail latch-type dynamic comparator

with a preamplifier [2]. The preamplifier’s mechanism is

that when clock ϕ is low, the output nodes are precharged

to power supply. Then ϕ goes high, and the output are

discharged by the transistors M1, M2 and M3. The

following latch is used to shape and detect the different

discharging speed of the two nodes owning to different

input voltage. However, the dynamic comparator suffers

from large input offset due to the transistor’s mismatch,

especially when CMOS processes scale down. Offset

cancellation or calibration techniques are highly required.

LQ

LQ

RXW

RXW

0 0

0

0S

0S

0

Figure 1. Conventional latched dynamic comparator with

a preamplifier [2]

The method reported in [3] does not need static power

dissipation and refresh process, but requires configurable

capacitor arrays, memories and logic controllers. This

results in lower speed and larger area for a high

cancellation resolution. The current cancellation

technique introduced in [4] exploits additional one pair of

compensation input transistors and a charge pump. Its

weakness lies in a long calibrating time due to the

successive approximation operation and a large area for

the auxiliary circuits. A dynamic offset cancellation

technique, by sampling the mismatches at the drain

terminal of the input transistors, is proposed in [5]. A large

bridging capacitor is required to store the mismatches and

cancel the offset finally. This capacitor increases the

differential load, thus reducing the gain of the dynamic

preamplifier. Another dynamic offset cancellation

technique, by storing offset at the source terminal of the

input transistors, is reported in [6]. In this method,

however only the threshold mismatch is suppressed and

the bias voltage 



had better to be set low to get a low

offset voltage, leading to a long comparison time.

In this paper, by storing offset at the gate terminal of

the input transistors, a low-offset and small-area dynamic

preamplifier with input offset-cancellation technique, is

proposed. The offset resulting from both threshold voltage

132

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