树莓派主控BCM2835详细解读：地址映射与接口

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本文档详细介绍了树莓派（Raspberry Pi）的主控芯片BCM2835的相关知识，由Broadcom Corporation于2012年发布。BCM2835是一款专为嵌入式系统设计的高性能ARM处理器，集成了多种外围接口，如UART、SPI以及DMA控制器，使得树莓派在低成本、低功耗平台上实现丰富的功能。 1. **概述** BCM2835的核心部分是一颗ARM1176JZF-S微处理器，运行在600MHz频率下，具有32位处理器架构和128MB的LPDDR2 SDRAM内存。该芯片的设计旨在提供基本的计算能力，同时优化了与外部设备的通信能力，包括通过总线接口进行的数据传输。 2. **地址映射** - **虚拟地址**：标准Linux内核支持下，BCM2835使用ARM的虚拟地址空间进行内存管理，这有助于提高系统的灵活性和兼容性。 - **物理地址**：芯片内部的硬件逻辑有自己的物理地址，用于直接访问存储器和外设。 - **总线地址**：用于连接外部设备，如GPIO、DMA等，这些地址通常映射到特定的硬件模块。 3. **外围接口** - **辅助接口**：文档详述了两个辅助接口， UART1和SPI1，以及SPI2。它们分别用于串行通信和通用串行接口，支持中断和长数据流处理。 - **MiniUART**：是BCM2835提供的小型UART，用于简单的串口通信，包括其实施细节和寄存器结构。 - **Universal SPI Master (2x)**：作为全双工SPI接口，支持两个独立的SPI通道，包括中断机制、长数据流处理以及详细的寄存器配置。 4. **视频和显示控制器（BSC）** - BSC负责视频信号的输出，提供了视频帧缓冲区和图形处理功能。它支持10位地址寻址，对于树莓派的HDMI和复合视频输出至关重要。 5. **DMA控制器** - DMA（Direct Memory Access）控制器用于高速数据传输，无需CPU干预，减轻了CPU的负担。文档列出了DMA控制器的各个寄存器及其地址映射，还涵盖了AXI Burst模式，即连续数据传输技术，以及错误处理机制。总结来说，BCM2835是树莓派的灵魂，它集成的多种外围设备接口使得树莓派能够成为一个功能丰富的平台，广泛应用于物联网、嵌入式开发、教育和原型设计等领域。掌握这些接口和控制器的工作原理，对于利用树莓派进行硬件编程和扩展至关重要。

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 16

AUX_MU_SCRATCH Register (0x7E21 505C)

YNOPSIS

The

AUX_MU_SCRATCH

is a single byte storage.

Bit(s) Field Name Description Type

Reset

31:8

Reserved, write zero, read as don’t care

7:0 Scratch

One whole byte extra on top of the 134217728

provided by the SDC

R/W 0

AUX_MU_CNTL_REG Register (0x7E21 5060)

YNOPSIS

The

AUX_MU_CNTL_REG

provides access to some extra useful and nice features not

found on a normal 16550 UART .

Bit(s) Field Name Description Type

Reset

31:8

Reserved, write zero, read as don’t care

CTS assert

level

This bit allows one to invert the CTS auto flow

operation polarity.

If set the CTS auto flow assert level is low*

If clear the CTS auto flow assert level is high*

R/W 0

RTS assert

level

This bit allows one to invert the RTS auto flow

operation polarity.

If set the RTS auto flow assert level is low*

If clear the RTS auto flow assert level is high*

R/W 0

5:4

RTS AUTO

flow level

These two bits specify at what receiver FIFO level the

RTS line is de-asserted in auto-flow mode.

00 : De-assert RTS when the receive FIFO has 3

empty spaces left.

01 : De-assert RTS when the receive FIFO has 2

empty spaces left.

10 : De-assert RTS when the receive FIFO has 1

empty space left.

11 : De-assert RTS when the receive FIFO has 4

empty spaces left.

R/W 0

Enable

transmit Auto

flow-control

using CTS

If this bit is set the transmitter will stop if the CTS

line is de-asserted.

If this bit is clear the transmitter will ignore the status

of the CTS line

R/W 0

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 17

Enable receive

Auto flow-

control using

RTS

If this bit is set the RTS line will de-assert if the

receive FIFO reaches it 'auto flow' level. In fact the

RTS line will behave as an RTR (Ready To Receive)

line.

If this bit is clear the RTS line is controlled by the

AUX_MU_MCR_REG register bit 1.

R/W 0

Transmitter

enable

If this bit is set the mini UART transmitter is enabled.

If this bit is clear the mini UART transmitter is

disabled

R/W 1

Receiver

enable

If this bit is set the mini UART receiver is enabled.

If this bit is clear the mini UART receiver is disabled

R/W 1

Receiver enable

If this bit is set no new symbols will be accepted by the receiver. Any symbols in progress of

reception will be finished.

Transmitter enable

If this bit is set no new symbols will be send the transmitter. Any symbols in progress of

transmission will be finished.

Auto flow control

Automatic flow control can be enabled independent for the receiver and the transmitter.

CTS auto flow control impacts the transmitter only. The transmitter will not send out new

symbols when the CTS line is de-asserted. Any symbols in progress of transmission when

the CTS line becomes de-asserted will be finished.

RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is

incorrect and should be RTR (Ready to Receive). The receiver will de-asserted the RTS

(RTR) line when its receive FIFO has a number of empty spaces left. Normally 3 empty

spaces should be enough.

If looping back a mini UART using full auto flow control the logic is fast enough to allow

the RTS auto flow level of '10' (De-assert RTS when the receive FIFO has 1 empty space

left).

Auto flow polarity

To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed.

This should allow the mini UART to interface with any existing hardware flow control

available.

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 20

2.3 Universal SPI Master (2x)

The two universal SPI masters are secondary low throughput

SPI interfaces. Like the UART

the devices needs to be enabled before they can be used. Each SPI master has the following

features:

• Single beat bit length between 1 and 32 bits.

• Single beat variable bit length between 1 and 24 bits

• Multi beat infinite bit length.

• 3 independent chip selects per master.

• 4 entries 32-bit wide transmit and receive FIFOs.

• Data out on rising or falling clock edge.

• Data in on rising or falling clock edge.

• Clock inversion (Idle high or idle low).

• Wide clocking range.

• Programmable data out hold time.

• Shift in/out MS or LS bit first

A major issue with an SPI interface is that there is no SPI standard in any form. Because the

SPI interface has been around for a long time some pseudo-standard rules have appeared

mostly when interfacing with memory devices. The universal SPI master has been developed

to work even with the most 'non-standard' SPI devices.

2.3.1 SPI implementation details

The following diagrams shows a typical SPI access cycle. In this case we have 8 SPI clocks.

1 Bit time

Set-up Operate

Hold

(optional)

Idle

Clk

Cs_n

One bit time before any clock edge changes the CS_n will go low. This makes sure that the

MOSI signal has a full bit-time of set-up against any changing clock edges.

The operation normally ends after the last clock cycle. Note that at the end there is one half-

bit time where the clock does not change but which still is part of the operation cycle.

There is an option to add a half bit cycle hold time. This makes sure that any MISO data has

at least a full SPI bit time to arrive. (Without this hold time, data clocked out of the SPI

device on the last clock edge would have only half a bit time to arrive).

Again the SPIs themselves have no throughput limitations in fact they can run with an SPI clock of 125 MHz.

But doing so requires significant CPU involvement as they have shallow FIFOs and no DMA support.

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