PCI Express M.2规格 v4.0版1.0 - 2020年11月发布

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PCI Express (PCIe) M.2规格修订4.0版本1.0，发布日期为2020年11月5日，是PCI-SIG（PCI标准促进组织）制定的一项关键行业标准，用于规范现代计算机系统中的高速接口。M.2插槽是一种紧凑型模块化设计，专为固态硬盘（SSD）和其他扩展卡提供高速数据传输。这个版本的主要更新可能包括更高的带宽、更低的延迟以及更强大的连接能力，从而提升系统的整体性能。 PCIe 4.0标准相较于前一代提升了大约两倍的理论传输速率，达到最高16 GT/s（吉比特每秒），这使得M.2设备能够更快地读写数据。它采用更先进的信号技术，如Gen4 x4 lanes，支持双向通信，允许设备和主板之间实现更高效的双向数据交换。同时，为了适应不断发展的硬件需求，该规格还可能包括电源管理优化，提高能源效率。然而，重要的是要注意，PCI-SIG提供的这份规范并不保证其准确性或最新性，用户应直接从官方获取最新版本以确保与实际应用的兼容性和最佳性能。若在使用过程中遇到问题或需要了解关于PCIe M.2规格的更多信息，可以通过访问PCI-SIG官网（www.pcisig.com）或联系他们的客户服务（电话：503-619-0569，传真：503-644-6708，电子邮件：administration@pcisig.com 或 techsupp@pcisig.com）获取帮助。此外，该文档包含了免责声明，声明所有关于此规范的责任都由PCI-SIG承担，包括但不限于对文档内容的准确性、无侵权性或适合特定用途的保证。任何使用此规范而产生的问题，PCI-SIG均不承担责任，且未明确授予用户关于知识产权的许可。因此，在设计和实施基于PCIe M.2标准的产品时，必须确保符合所有相关法律法规和专利要求。

PCI Express M.2 Specification 
November 5, 2020 
PCI Express M.2 Specification  |  16 
Revision 4.0, Version 1.0 
Figure 2-66.  H3.2-D1 - Stack-up Top Mount Double-sided Add-in Card for 1.20 Maximum Top-side 
Component Height ................................................................................................................. 91 
Figure 2-67.  H3.2-D2 - Stack-up Top Mount Double-sided Add-in Card for 1.35 Maximum Top-side 
Component Height ................................................................................................................. 91 
Figure 2-68.  H3.2-D3 - Stack-up Top Mount Double-sided Add-in Card for 1.5 Maximum Top-side 
Component Height ................................................................................................................. 92 
Figure 2-69.  H4.2-D5 - Stack-up Top Mount Double-sided Add-in Card for 1.5 Maximum Top-side 
Component Height with  1.5 Maximum Bottom-side Component Height .............................. 92 
Figure 2-70.  H4.2-D8-P Stack-up Top Mount Double-sided Add-in Card for 3.2mm +0 / -0.5 Top-side 
dimension and 1.5 Maximum Bottom-side Component Height ............................................. 92 
Figure 2-71.  Example of Top Mount Motherboard Land Pattern - Key B Shown ....................................... 93 
Figure 2-72.  Mid-mount (In-line) Connector Dimensions ........................................................................... 94 
Figure 2-73.  Mid-mount (In-line) System Length ........................................................................................ 95 
Figure 2-74.  Stack-up Mid-mount (In-line) Single-sided (S1) Add-in Card for 1.2 Maximum  
Component Height ................................................................................................................. 96 
Figure 2-75.  Stack-up Mid-mount (In-line) Single-sided (S2) Add-in Card for 1.35 Maximum  
Component Height ................................................................................................................. 96 
Figure 2-76.  Stack-up Mid-mount (In-line) Single-sided (S3) Add-in Card for 1.5 Maximum  
Component Height ................................................................................................................. 96 
Figure 2-77.  Stack-up Mid-mount (In-line) Double-sided (D1) Add-in Card for 1.2 Maximum  
Top-side Component Height .................................................................................................. 97 
Figure 2-78.  Stack-up Mid-mount (In-line) Double-sided (D2) Add-in Card for 1.35 Maximum  
Top-side Component Height .................................................................................................. 97 
Figure 2-79.  Stack-up Mid-mount (In-line) Double-sided (D3) Add-in Card for 1.5 Maximum  
Top-side Component Height .................................................................................................. 97 
Figure 2-80.  Stack-up Mid-mount (In-line) Double-sided (D4) Add-in Card for 1.5 Maximum  
Top-side Component Height .................................................................................................. 98 
Figure 2-81.  Stack-up Mid-mount (In-line) Double-sided (D5) Add-in Card for 1.5 Maximum  
Top-side and Bottom-side Component Height ....................................................................... 98 
Figure 2-82.  Example of Mid-mount Motherboard Land Pattern Diagram – Key B Shown ....................... 99 
Figure 2-83.  Connector Key ..................................................................................................................... 100 
Figure 2-84.  M.2 Connector Keying Diagram ........................................................................................... 101 
Figure 2-85.  Dual Add-in Card Key Scheme Example ............................................................................. 102 
Figure 2-86.  Mid-mount Add-in Card Mounting Interface ......................................................................... 103 
Figure 2-87.  Single-sided Top Mount Solder-down Stand-off .................................................................. 104 
Figure 2-88.  Elevated Single-sided Top Mount Solder Stand-off ............................................................. 104 
Figure 2-89.  Low Profile Double-sided Top Mount Solder-down Stand-off .............................................. 105 
Figure 2-90.  Double-sided Top Mount Solder-down Stand-off ................................................................. 105 
Figure 2-91.  Elevated Double-sided Top Mount Solder-down Stand-off ................................................. 105 
Figure 2-92.  Flat Stand-off ........................................................................................................................ 106 
Figure 2-93.  Shouldered Stand-off ........................................................................................................... 107 
Figure 2-94.  Screw Guidelines ................................................................................................................. 107 

PCI Express M.2 Specification 
November 5, 2020 
PCI Express M.2 Specification  |  17 
Revision 4.0, Version 1.0 
Figure 2-95.  Wafer-head Style M3 Screw ................................................................................................ 108 
Figure 2-96.  M3 Screw with Tapered Shaft .............................................................................................. 108 
Figure 2-97.  Wafer-head Style M2 Screw ................................................................................................ 109 
Figure 2-98.  Flat-head Style M3 Screw .................................................................................................... 109 
Figure 3-1.  CLKREQ# Clock Control Timings ........................................................................................ 121 
Figure 3-2.  Power-up Timing Sequence for an Adapter Powered from System Power Rail ................. 122 
Figure 3-3.  SDIO Reset Sequence ......................................................................................................... 125 
Figure 3-4.  SDIO Power-up Sequence ................................................................................................... 126 
Figure 3-5.  UART Frame Format ........................................................................................................... 127 
Figure 3-6.  Typical PCM Transaction Timing Diagram .......................................................................... 128 
Figure 3-7.   Supplemental NFC Signal Connection Example ................................................................. 130 
Figure 3-8.  Typical LED Connection Example in Platform/System ........................................................ 131 
Figure 3-9.  Type 2226 SDIO Based Module-side Pinout ....................................................................... 139 
Figure 3-10.  Type 1216 SDIO Based Module-side Pinout ....................................................................... 140 
Figure 3-11.  Type 3026 DisplayPort Pinouts Extension Over an SDIO Based Module-side Pinout........ 141 
Figure 3-12.  Power-up Timing Sequence for a WWAN Specific Adapter Powered by a Direct V
BAT
 
Connection ........................................................................................................................... 146 
Figure 3-13.  Typical SIM Detect Circuit Implementation .......................................................................... 149 
Figure 3-14.  Example of a Connection of the GNSS Signals in a Platform Using M.2 Adapter .............. 152 
Figure 3-15.  WAKE_ON_WWAN# Signal ................................................................................................ 153 
Figure 3-16.  Power Loss Sequencing Behavior for Socket 2 ................................................................... 159 
Figure 3-17.  Power Loss Sequencing Behavior for Socket 3 ................................................................... 172 
Figure 3-18.  Type 1620 BGA Module-side Ballmap (Top View) .............................................................. 185 
Figure 3-19.  Type 1620 BGA Module-side Ballmap Surrounded by  Type 2024, Type 2228, and Type 
2828 Module-side Ballmaps (Top View) .............................................................................. 186 
Figure 3-20.  Type 1113 BGA Module-side Ballmap (Top View) .............................................................. 187 
Figure 4-1.  Power-on Sequencing Examples ......................................................................................... 192 
Figure 4-2.  Power-off Sequencing Examples ......................................................................................... 193 
Figure 4-3.  8.0 GT/s M.2 Add-in Card Transmitter Path Compliance Eye Diagram .............................. 196 
Figure 4-4.  8.0 GT/s System Board Transmitter Path Composite Compliance Eye Diagram ............... 199 
Figure 4-5.  16.0 GT/s System Board Transmitter Path Composite Compliance Eye Diagram ............. 204 
Figure 5-1.  Type 2226 LGA Pinout Using SDIO Based Socket 1 Pinout on Platform ........................... 224 
Figure 5-2.  Type 1216 LGA Pinout Using SDIO Based Socket 1 Pinout on Platform ........................... 224 
Figure 5-3.  Type 3026 LGA Pinout Using SDIO Based Socket 1 and DisplayPort  
Based Socket 1 Pinout on Platform ..................................................................................... 225 
Figure 5-4.  Type 1620 BGA Pinout on Platform (Top View) .................................................................. 226 
Figure 5-5.  Type 1620 BGA Module-side Pinout Surrounded by Type 2024, Type 2228,  
and Type 2828 Platform-side Pinout (Top View) ................................................................. 227 
Figure 5-6.  Type 1113 BGA Socket Map on Platform (Top View) ......................................................... 228 

PCI Express M.2 Specification 
November 5, 2020 
PCI Express M.2 Specification  |  18 
Revision 4.0, Version 1.0 
Figure 6-1.  UART and PCM Signal Direction and Signal Name Changes ............................................. 230 
Figure 6-2.  PCIe Signal Direction and Signal Name Changes ............................................................... 231 
Figure 6-3.  COEX_TXD and COEX_RXD Signal Direction ................................................................... 231 
Figure 6-4.  Suggested Motherboard and Add-in Card Signals and Ground Pad Layout Guideline ...... 233 
Figure 6-5.  Suggested Ground Void for Add-in Card Simulation ........................................................... 234 
Figure 6-6.  Suggest Ground Void for Main Board .................................................................................. 234 
Figure 6-7.  Top Mount Add-in Card Test Fixture PCB Layout ............................................................... 235 
Figure 6-8.  Top Mount Motherboard Test Fixture PCB .......................................................................... 236 
Figure 6-9.  Top Mount Connector Test Fixture ...................................................................................... 237 
Figure 6-10.  Mid-mount Connector Test Fixture ...................................................................................... 238 
Figure 6-11.  Mid-mount Add-in Card Test Fixture PCB Layout ............................................................... 238 
Figure 6-12.  Mid-mount Motherboard Test Fixture PCB .......................................................................... 239 
Figure 6-13.  Detail of Top-side SMA End Launch Connector Pad........................................................... 239 
Figure 6-14.  Ground Void on Backside .................................................................................................... 240 
Figure 6-15.  Detail of Mid-mount Vias on Top-side Motherboard ............................................................ 241 
Figure 6-16.  Detail of Ground Void on Mid-mount Bottom Side Motherboard ......................................... 241 
Figure 6-17.  Differential Insertion Loss Limits for 16.0 GT/s Operation ................................................... 243 
Figure 6-18.  Differential Return Loss Limits for 16.0 GT/s Operation ...................................................... 244 
Figure 6-19.  Differential Near End and Far End Crosstalk Limits for 16.0 GT/s Operation ..................... 244 
Figure 6-20.  Near-End Crosstalk Victim and Aggressors for the PCIe Based Pinout (Socket 2 & 3) ...... 245 
Figure 6-21.  Far-End Crosstalk Victim and Aggressors for the PCIe Based Pinout ................................ 245 
Figure 6-22.  Suggested Add-in Card Signals and Ground Pad Layout Guideline (Top View and Side 
Cross-section View) ............................................................................................................. 248 
Figure 6-23.  Suggested Ground Void for Add-in Card Simulation ........................................................... 248 
Figure 6-24.  Suggested Ground Void for Add-in Card ............................................................................. 249 
Figure 6-25.  Suggested Ground Void for Main Board .............................................................................. 249 
Figure 6-26.  Top Mount Add-in Card Test Fixture PCB Layout ............................................................... 250 
Figure 6-27.  Top Mount Motherboard Test Fixture PCB .......................................................................... 251 
Figure 6-28.  VSWR Test Setup for Receptacle RF Connector ................................................................ 251 
Figure 6-29.  Contact Resistance Measurement Definitions ..................................................................... 252 
Figure 6-30.  Prepared Wires .................................................................................................................... 253 
Figure 6-31.  Prepared Wire with Plug ...................................................................................................... 253 
Figure 6-32.  Example View of Notebook Motherboard ............................................................................ 263 
Figure 6-33.  Example View of Edge Vents ............................................................................................... 263 
Figure 6-34.  Example View of Bottom Vents (vent opening where inside boards are visible  
through the opening) ............................................................................................................ 263 
Figure 6-35.  Example View of Region Over Adapters ............................................................................. 264 
Figure 6-36.  Example View of Hot Spot Over Adapters ........................................................................... 264 
Figure 6-37.  Example View of Motherboard for Thin Platform Notebook with Fan .................................. 267 

PCI Express M.2 Specification 
November 5, 2020 
PCI Express M.2 Specification  |  20 
Revision 4.0, Version 1.0 
List of Tables 
Table 2-1.  Optional Adapter Configurations ............................................................................................ 33 
Table 2-2.  General Tolerance ................................................................................................................. 34 
Table 2-3.  Key Location/Pin Block Dimensions for Keys A to F ............................................................. 51 
Table 2-4.  Key Location/Pin Block Dimensions for Keys G to M ............................................................ 51 
Table 2-5.  RF Connector Physical Characteristics ................................................................................. 76 
Table 2-6.  RF Connector Mechanical Requirements .............................................................................. 76 
Table 2-7.  RF Connector Electrical Requirements ................................................................................. 77 
Table 2-8.  RF Connector Environmental Requirements ......................................................................... 77 
Table 2-9.  Recommended Antenna Function Allocation Table............................................................... 78 
Table 2-10.  Connector/Adapter Height Supported Matrix ......................................................................... 81 
Table 2-11.  Connector Physical Requirements......................................................................................... 82 
Table 2-12.  Connector Environmental Requirements ............................................................................... 83 
Table 2-13.  Connector Electrical Requirements ....................................................................................... 83 
Table 2-14.  Stand-off Height Descriptor Table........................................................................................ 106 
Table 3-1.  Socket 1 System Interface Signals and Voltage Table ........................................................ 113 
Table 3-2.  M.2 Clocking Architecture Requirements ............................................................................ 118 
Table 3-3.  M.2 Common Clock Architecture Details ............................................................................. 119 
Table 3-4.  Power-up CLKREQ# Timings .............................................................................................. 121 
Table 3-5.  Power-up and Additional PERST Timing Variables ............................................................. 123 
Table 3-6.  DP_MLDIR Pin Termination ................................................................................................. 124 
Table 3-7.  SDIO Reset and Power-up Timing....................................................................................... 126 
Table 3-8.  Simple Indicator Protocol for LED States ............................................................................ 131 
Table 3-9.  Radio Operational States ..................................................................................................... 133 
Table 3-10.  Wireless Disable Pin Mode and Function Assignment ........................................................ 133 
Table 3-11.  SDIO Based Add-in Card Pinouts (Key E) ........................................................................... 136 
Table 3-12.  DisplayPort Based Add-in Card Pinouts (Key A) ................................................................. 137 
Table 3-13.  Socket 1 Add-in Card Pinouts (Key A-E) ............................................................................. 138 
Table 3-14.  Socket 2 System Interface Signal Table .............................................................................. 142 
Table 3-15.  GPIO Pin Function Assignment per Port Configuration ....................................................... 151 
Table 3-16.  Audio Pin Mode and Function Assignment .......................................................................... 153 
Table 3-17.  Antenna Control Pin Mode and Function Assignment ......................................................... 154 
Table 3-18.  Socket 2 Add-in Card Configuration .................................................................................... 156 
Table 3-19.  Socket 2 Key B SSIC-based WWAN Adapter Pinout .......................................................... 160 
Table 3-20.  Socket 2 Key B USB3.1 Gen1-based WWAN Adapter Pinout ............................................ 161 
Table 3-21.  Socket 2 Key B PCIe-based WWAN Adapter Pinout........................................................... 162 