深入教程：ISE仿真器ISim全面指南

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"ISE仿真经典教程，这是一份深入的ISE开发入门教程，特别关注于ISE自带的仿真器ISIM的介绍。" 这篇教程是针对Xilinx的ISE(Integrated Software Environment)设计工具的深入指南，主要关注其内置的仿真器ISim。ISim是一款强大的软件，用于验证基于Xilinx FPGA或 CPLD 设计的功能正确性。本教程适用于初学者，旨在提供详细的设计流程以及ISim的使用方法。 ISE是Xilinx提供的一个综合型开发环境，它集成了逻辑设计、综合、仿真、配置等多个步骤，使得用户能够在一个统一的平台上完成FPGA的设计工作。教程中的内容可能涵盖以下方面： 1. **ISE设计流程**：从创建项目、输入设计代码（VHDL或Verilog）到编译、仿真，最后到生成配置文件，这一系列步骤的详细说明，帮助新手理解整个设计过程。 2. **ISim基础**：ISim的用户界面介绍，包括如何设置仿真环境、添加源文件、定义激励信号、编写测试平台等。 3. **仿真操作**：启动和控制仿真，如设置仿真时间范围、观察波形、触发条件、断点等，以及如何使用ISim进行时序分析。 4. **错误调试**：ISim在仿真过程中如何显示错误和警告，以及如何定位和修复问题，提升设计效率。 5. **高级功能**：可能包括高级仿真技巧，如使用覆盖分析、性能指标测量、多进程同步等。 6. **实例演示**：通过具体的例子，让学习者实践设计和仿真的步骤，加深理解。请注意，Xilinx文档通常会定期更新，以包含新功能和改进，因此UG682文档可能随着时间的推移而有所变化。尽管Xilinx不承担提供技术支持或更新的责任，但这份教程仍能提供基础的指导，帮助用户理解和掌握ISE与ISim的使用。在使用此教程时，务必遵守Xilinx的使用条款，未经许可，不得复制、分发或以其他方式传播该文档。同时，Xilinx对由于使用文档导致的任何问题或损失不承担责任，用户需自行承担设计风险。尽管如此，Xilinx可能在任何时候根据需要更新文档，用户应关注最新的版本以获取最准确的信息。

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 3

UG682 (v1.0) April 27, 2009

Chapter 2

Using ISE Simulator from ISE Project

Navigator

Overview of ISim ISE Integrated Flow

The Xilinx

ISE software provides an integrated flow with the Xilinx ISE Simulator (ISim)

that allows simulations to be launched directly from the Xilinx Project Navigator (ISE). All

simulation commands that prepare the ISim simulation are generated by ISE Project

Navigator and automatically run in the background when simulating a design using this

flow.

Getting Started

Software Requirements

To use this tutorial, you must install the following software:

1. ISE WebPACK™ 11, or

2. One of the ISE Design Suite 11 Editions (Logic, DSP, Embedded, System)

For more information about installing Xilinx

software, see the ISE Release Notes and Installation

Guide at: http://www.xilinx.com/support/software_manuals.htm

Installing the Tutorial Design Files

Design files for this tutorial can be downloaded from:

http://www.xilinx.com/support/techsup/tutorials/tutorials11.htm

After you have downloaded the tutorial project files from the Web, unzip them into an

easily accessible directory with full read and write permissions.

The contents of the tutorial project files are as follows:

• sources: Folder containing all the HDL files necessary for a functional simulation of

the design.

• scripts: Folder containing incomplete script files to run the simulation. These script

files will be completed as you go through the tutorial.

• completed: Folder containing completed script, simulation and wave configuration

files, as well as a completed ISE 11 project of the tutorial design, for comparison

purposes.

4 www.xilinx.com ISE Simulator (ISim) In-Depth Tutorial

UG682 (v1.0) April 27, 2009

Design Description

The ISim In-Depth Tutorial provides a design which the reader can use to become familiar

performing some basic simulation steps while using the ISim software.

The tutorial design is a simple demonstration of the Dynamic Reconfiguration feature of

the Virtex

-5 Digital Clock Manager (DCM).

Using the Virtex-5 DCM, the design generates an output clock using the following

relationship:

Output Clock = Input Clock * (Multiplier / Divider)

Using the Dynamic Reconfiguration Ports (DRP) in the DCM, the design allows the user to

re-define the Multiplier and Divider parameters to generate different output frequencies.

Functional Blocks

The tutorial design consists of the following functional blocks.

• drp_dcm (drp_dcm.vhd)

Virtex-5 DCM macro with internal feedback, frequency controlled output, duty-cycle

correction, and Dynamic Reconfiguration ability.

The CLKFX_OUT output provides a clock that is defined by the following

relationship:

CLKFX_OUT = CLKIN_IN * (Multiplier/Divider)

For example, using a 100 MHz input clock, setting the Multiplier factor to 6, and

Divider factor to 5, produces a 120 MHz CLKFX_OUT output clock.

Using the DRP ports of the DCM, the Multiplier (M) and Divider (D) parameters can

be dynamically redefined to produce different CLKFX_OUT frequencies. For the

purposes of this tutorial, it suffices to show how the Multiply and Divide parameters

are provided to the DCM via the 16-bit wide DI_IN port:

DI_IN[15:8] = M – 1

DI_IN[7:0] = D – 1

For example, for an M/D factor of 6 / 5, DI_IN = 0504h.

• drp_stmach (drp_stmach.vhd)

This module describes a Dynamic Reconfiguration Controller. The DRP controller

asserts and monitors the DCM DRP signals in order to perform a dynamic

reconfiguration cycle.

A dynamic reconfiguration cycle is started by asserting the drp_start signal. Following

this step, the DRP Controller asserts the appropriate DCM DRP pins in order to

complete a full Dynamic Reconfiguration cycle.

Signal drp_done indicates a successful completion of a dynamic reconfiguration cycle.

• drp_demo (drp_demo.vhd)

This is the top module of the tutorial design which connects the DCM macro and the

DRP controller modules to the external I/O ports.

• drp_demo_tb (drp_demo_tb.vhd)

Self-checking HDL test bench. Refer to Design Self-Checking Test Bench for more

information.

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 5

UG682 (v1.0) April 27, 2009

Simulating the Design

Design Self-Checking Test Bench

To test the functionality of this design, a self-checking test bench has been provided. (Refer to

source file drp_demo_tb.vhd in the sources folder.) A self-checking test bench contains a validation

routine or function that compares sampled values from the simulation against expected results. The

self-checking test bench provided for this design performs the following functions.

• Generates a 100 MHz input clock for the design system clock (clk_in).

• Performs four different tests in order to dynamically change the output frequency of

the design. In each test, a DRP cycle is started (using the drp_start signal) to set the

output clock to a different frequency. The following table shows the desired output

frequency and Multiplier/Divider parameters used for each test.

• In each test, the test bench will compare the expected clock period and the clock period

measured during simulation. Based on the comparison results, messages to the simulator will

be written indicating success or failure.

• Upon completion of the simulation, a summary report is provided, listing which tests

passed or failed.

Note:

For more details on the functionality of this design, refer to the in-line comments included in

the sources of the design.

Simulating the Design

Thanks to an intuitive integrated flow, you can easily and quickly perform behavioral and

timing simulations of your design in the ISE Project Navigator software. Using the

integrated flow, you can quickly set up simulation properties and launch the ISim software

with a few clicks of the mouse.

We shall demonstrate how ISim can be launched using the ISE Project Navigator by first

creating an ISE project for the tutorial design. We will then set some behavioral simulation

properties and launch the ISim simulator to perform a behavioral simulation of the design.

Creating a Project in ISE Project Navigator

We will use the New Project Wizard in ISE Project Navigator to quickly create an ISE

project for the tutorial design.

Note:

Read Installing the Tutorial Design Files to obtain the files required for this design.

Using New Project Wizard

Follow these steps to create an ISE project using the New Project Wizard.

1. Launch the ISE Project Navigator by double-clicking on the Xilinx ISE 11 desktop icon.

Table 2-1: Desired Output Frequency and Multiplier/Divider Parameters Used For

Each Test

Test Freq. (MHz) Period (ps) Multiplier (M) Divider (D)

17513,3323 4

2 120 8,332 6 5

3 250 4000 5 2

4 400 2,500 4 1

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