ModelSim SE Reference: FPGA设计与HDL仿真教程

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本资源是《ModelSim®SEReferenceManual》软件版本6.4a的用户参考手册，由Mentor Graphics Corporation于1991年至2008年发布。它主要关注FPGA逻辑设计和硬件描述语言（Hardware Description Language, HDL）的仿真，特别适用于初学者进行Modelsim软件的入门学习。在该手册中，读者可以找到关于如何使用Modelsim进行数字系统设计和验证的重要信息。ModelSim是一款功能强大的行为级模拟器，常用于VHDL或Verilog等HDL语言的仿真，这些是用于描述硬件电路行为的高级编程语言。通过这个工具，设计人员能够在软件中构建、测试和调试他们的设计模型，以确保逻辑功能的正确性和性能。章节可能包括以下几个关键知识点： 1. **安装与配置**：手册会指导用户如何下载、安装和配置ModelSim环境，以便与IDE集成或者作为独立的命令行工具使用。 2. **HDL基础**：介绍了VHDL和Verilog语言的基本语法和结构，以及如何编写基本的模块、进程和接口描述。 3. **原理与流程**：详细阐述了仿真过程，包括波形分析、时序图查看、覆盖率分析等核心功能的使用方法。 4. **高级特性**：可能涵盖高级仿真技术，如时钟周期准确度调整、信号断言和断开、以及并行和流水线仿真等。 5. **故障排查与调试**：提供解决常见问题的技巧，如设置断点、观察寄存器值变化、处理模拟和行为级错误等。 6. **模型库与案例研究**：可能包含预设的模型库，以及针对不同应用领域的示例设计，帮助用户快速上手。 7. **许可证与法律注意事项**：强调了软件使用协议的重要性，包括复制和分发的限制，以及与Mentor Graphics公司签订的销售和许可协议条款。这本手册是FPGA设计人员的宝贵资源，对于理解和掌握Modelsim这款重要的硬件仿真工具具有不可替代的作用。无论是初次接触HDL还是希望提升现有技能的工程师，都能从中获得深入的理解和实践指导。务必遵守版权规定，确保合法使用和分享这份资料。

ModelSim SE Reference Manual, v6.4a

Syntax and Conventions

File and Directory Pathnames

Several ModelSim commands have arguments that point to files or directories. For example, the

-y argument to vlog specifies the Verilog source library directory to search for undefined

modules. Spaces in file pathnames must be escaped or the entire path must be enclosed in

quotes. For example:

vlog top.v -y C:/Documents\ and\ Settings/projects/dut

vlog top.v -y "C:/Documents and Settings/projects/dut"

Design Object Names

Design objects are organized hierarchically. Each of the following objects creates a new level in

the hierarchy:

• VHDL — component instantiation statement, block statement, and package

• Verilog — module instantiation, named fork, named begin, task and function

• SystemVerilog — class, package, program, and interface

• SystemC — module instantiation

Object Name Syntax

The syntax for specifying object names in ModelSim is as follows:

[<datasetName><datasetSeparator>][<pathSeparator>][<hierarchicalPath>]

<objectName>[<elementSelection>]

where

• datasetName — is the logical name of the WLF file in which the object exists. The

currently active simulation is the “sim” dataset. Any loaded WLF file is referred to by

the logical name specified when the WLF file was loaded. Refer to the chapter

“Recording Simulation Results With Datasets” in the User’s Manual for more

information.

• datasetSeparator — is the character used to terminate the dataset name. The default is

’:’, though a different character (other than ’\’) may be specified as the dataset separator

via the DatasetSeparator variable in the modelsim.ini file. The default is ':'. This

character must be different than the pathSeparator character.

• pathSeparator — is the character used to separate hierarchical object names. Normally,

'/' is used for VHDL and '.' is used for Verilog, although other characters (except '\') may

be specified via the PathSeparator variable in the modelsim.ini file. This character must

ModelSim SE Reference Manual, v6.4a

Syntax and Conventions

File and Directory Pathnames

A relative name does not start with a path separator and may or may not include a dataset name

or a hierarchical path (e.g., u1/data or view:clk). A relative name is relative to the current

context in the current or specified dataset.

A fully-rooted name starts with a path separator and includes a hierarchical path to an object

(e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-level design unit

name can be unspecified (e.g., /u1/clk). In this case, the first top-level instance in the design is

assumed.

An absolute name is an exactly specified hierarchical name containing a dataset name and a

fully rooted name (e.g., sim:/top/u1/clk).

The current dataset is used when accessing objects where a dataset name is not specified as part

of the name. The current dataset is determined by the dataset currently selected in the Structure

window or by the last dataset specified in an environment.

The current context in the current or specified dataset is used when accessing objects with

relative or simple names. The current context is either the current process, if any, or the current

instance if there is no current process or the current process is not in the current instance. The

situation of the current process not being in the current instance can occur, for example, by

selecting a different instance in the Structure tab or by using the environment to set the current

context to a different instance.

Table 1-2 contains examples of various ways of specifying object names.

Table 1-2. Examples of Object Names

Object Name Description

clk specifies the object clk in the current context

/top/clk specifies the object clk in the top-level design unit.

/top/block1/u2/clk specifies the object clk, two levels down from the top-level

design unit

block1/u2/clk specifies the object clk, two levels down from the current

context

array_sig[4] specifies an index of an array object

{array_sig(1 to 10)} specifies a slice of an array object in VHDL or SystemC;

see Escaping Brackets and Spaces in Array Slices for more

information

{mysignal[31:0]} specifies a slice of an array object in Verilog or SystemC;

see Escaping Brackets and Spaces in Array Slices for more

information

record_sig.field specifies a field of a record, a C++ class or structure

member, or a C++ base class

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