TRINAMIC TMC2209：超静音步进电机驱动器

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"TMC2209_Datasheet_V103 英文.pdf" TMC2209是一款专为两相步进电机设计的超静音电机驱动集成电路，由TRINAMIC Motion Control GmbH & Co. KG制造。这款驱动器与多个传统驱动器及TMC2208兼容，提供了高级的StealthChop2斩波器技术，确保无噪音运行、最大效率以及最佳电机扭矩。其快速电流调节功能和可选的SpreadCycle相结合，实现了高动态运动控制的同时增加了稳定性。 TMC2209适用于各种应用，包括3D打印机、打印机和POS系统、办公自动化、纺织和缝纫机、闭路电视和安全设备、自动取款机和现金回收机、暖通空调系统以及电池供电设备。这些领域都得益于其安静、高效和动态性能的特性。该驱动器的核心特性包括： 1. **2.8A线圈电流（峰值）支持**：适合2相步进电机，连续工作电流可达2ARMS。 2. **精细微步进设置**：通过STEP/DIR接口支持8、16、32或64细分的微步进。 3. **MicroPlyer™插补**：实现256细分的平滑运行，提高精度。 4. **StealthChop2™**：独特的无声电机操作技术，显著降低运行噪声。 5. **SpreadCycle™**：高度动态的电机控制斩波器，提供快速响应和精确控制。 6. **StallGuard4™**：用于在StealthChop模式下进行负载和堵转检测，便于无传感器寻边。 7. **CoolStep™**：节能电流控制，最高可节省75%的能源。 8. **低RDSon，低发热**：LS和HS通道的导通电阻典型值在25°C时为170mΩ，减少热损耗。 9. **电压范围广泛**：支持4.75到29V DC的工作电压。 10. **低功耗待机模式**：符合待机能量规定，降低能耗。 11. **内置感应电阻选项**：无需外部感测电阻即可工作。 12. **被动制动、自由轮和自动关断**：提供电源管理功能。 13. **单线UART和OTP**：支持高级配置选项，如编程和个性化设置。 14. **集成脉冲发生器**：允许独立的运动控制。 15. **全面保护和诊断**：包括过流、过温等在内的多种保护机制。 16. **紧凑型QFN封装**：具有大的散热表面积，有助于提高散热性能。 TMC2209是那些需要无声、高效且动态控制步进电机的应用的理想选择，它的多功能性和高级特性使其在各种工业和消费电子设备中表现出色。

TMC2209 DATASHEET (Rev. 1.03 / 2019-JUN-26) 14

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An effect which might be perceived at medium motor velocities and motor sine wave peak currents

above roughly 2A peak is a slight sine distortion of the current wave when using SpreadCycle. It

results from an increasing negative impact of parasitic internal diode conduction, which in turn

negatively influences the duration of the fast decay cycle of the SpreadCycle chopper. This is, because

the current measurement does not see the full coil current during this phase of the sine wave,

because an increasing part of the current flows directly from the power MOSFETs’ drain to GND and

does not flow through the sense resistor. This effect with most motors does not negatively influence

the smoothness of operation, as it does not impact the critical current zero transition. The effect does

not occur with StealthChop.

3.6 Low Power Standby

Battery powered applications, and mains powered applications conforming to standby energy saving

rules, often require a standby operation, where the power-supply remains on, but current draw goes

down to a low value. The TMC2209 supports standby operation of roughly 2mW (at 12V supply), or

<1mW at 5V supply using a dedicated pin STANDYBY. Pull up STANDBY to VCC_IO to go to low power

standby. VCC_IO may be dropped down to 1.5V during standby. A high level on STANDBY will disable

the internal 5V regulator and at the same time switches off all internal units. Prior to going to

STANDBY, stop the motor, and allow it to enter standstill current, or switch off the motor completely.

When in STANDBY, inputs ENN and VREF have to be driven to a low level. VCC_IO shall remain active

in standby mode. All driver registers are reset to their power-up defaults after leaving standby mode.

3.7 Driver Protection and EME Circuitry

Some applications have to cope with ESD events caused by motor operation or external influence.

Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset

or even a destruction of the motor driver, depending on their energy. Especially plastic housings and

belt drive systems tend to cause ESD events of several kV. It is best practice to avoid ESD events by

attaching all conductive parts, especially the motors themselves to PCB ground, or to apply electrically

conductive plastic parts. In addition, the driver can be protected up to a certain degree against ESD

events or live plugging / pulling the motor, which also causes high voltages and high currents into

the motor connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the

dV/dt caused by ESD events. Larger capacitors will bring more benefit concerning ESD suppression,

but cause additional current flow in each chopper cycle, and thus increase driver power dissipation,

especially at high supply voltages. The values shown are example values – they may be varied

between 100pF and 1nF. The capacitors also dampen high frequency noise injected from digital parts

of the application PCB circuitry and thus reduce electromagnetic emission. A more elaborate scheme

uses LC filters to de-couple the driver outputs from the motor connector. Varistors in between of the

coil terminals eliminate coil overvoltage caused by live plugging. Optionally protect all outputs by a

varistor to GND against ESD voltage.

Full Bridge A

Full Bridge B

stepper

motor

OA1

OA2

OB1

OB2

Driver

470pF

100V

470pF

100V

470pF

100V

470pF

100V

Full Bridge A

Full Bridge B

stepper

motor

OA1

OA2

OB1

OB2

Driver

470pF

100V

470pF

100V

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

Fit varistors to supply voltage

rating. SMD inductivities

conduct full motor coil

current.

470pF

100V

470pF

100V

Varistors V1 and V2 protect

against inductive motor coil

overvoltage.

V1A, V1B, V2A, V2B:

Optional position for varistors

in case of heavy ESD events.

BRB

BRA

100nF

16V

100nF

16V

V1A

V1B

V2A

V2B

Figure 3.4 Simple ESD enhancement and more elaborate motor output protection

TMC2209 DATASHEET (Rev. 1.03 / 2019-JUN-26) 15

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4 UART Single Wire Interface

The UART single wire interface allows control of the TMC2209 with any microcontroller UART. It shares

transmit and receive line like an RS485 based interface. Data transmission is secured using a cyclic

redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can be

bridged without danger of wrong or missed commands even in the event of electro-magnetic

disturbance. The automatic baud rate detection makes this interface easy to use.

4.1 Datagram Structure

4.1.1 Write Access

UART WRITE ACCESS DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

0 … 63

sync + reserved

8 bit slave

address

RW + 7 bit

32 bit data

CRC

0…7

8…15

16…23

24…55

56…63

Reserved (don’t cares

but included in CRC)

SLAVEADDR=0…3

address

data bytes 3, 2, 1, 0

(high to low byte)

CRC

…

A sync nibble precedes each transmission to and from the TMC2209 and is embedded into the first

transmitted byte, followed by an addressing byte (0 to 3 for TMC2209, depending on address setting).

Each transmission allows a synchronization of the internal baud rate divider to the master clock. The

actual baud rate is adapted and variations of the internal clock frequency are compensated. Thus, the

baud rate can be freely chosen within the valid range. Each transmitted byte starts with a start bit

(logic 0, low level on SWIOP) and ends with a stop bit (logic 1, high level on SWIOP). The bit time is

calculated by measuring the time from the beginning of start bit (1 to 0 transition) to the end of the

sync frame (1 to 0 transition from bit 2 to bit 3). All data is transmitted bytewise. The 32 bit data

words are transmitted with the highest byte first.

A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud

rate). Maximum baud rate is f

CLK

/16 due to the required stability of the baud clock.

The slave address SLAVEADDR is selected by MS1 (bit 0) and MS2 (bit 1).

The communication becomes reset if a pause time of longer than 63 bit times between the start bits

of two successive bytes occurs. This timing is based on the last correctly received datagram. In this

case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of

bus idle time. This scheme allows the master to reset communication in case of transmission errors.

Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout

of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the

same way. This allows a safe re-synchronization of the transmission after any error conditions.

Remark, that due to this mechanism an abrupt reduction of the baud rate to less than 15 percent of

the previous value is not possible.

Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal

cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the

success of an initialization sequence or single write accesses. Read accesses do not modify the

counter.

UART

TMC2209 DATASHEET (Rev. 1.03 / 2019-JUN-26) 16

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The UART line must be logic high during idle state. Therefore, the power down function cannot be

assigned by the pin PDN_UART in between of transmissions. In an application using the UART

interface, set the desired power down function by register access and set pdn_disable in GCONF to

disable the pin function.

4.1.2 Read Access

UART READ ACCESS REQUEST DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

sync + reserved

8 bit slave address

RW + 7 bit register

address

CRC

0...7

8…15

16…23

24…31

Reserved (don’t cares

but included in CRC)

SLAVEADDR=0…3

CRC

…

The read access request datagram structure is identical to the write access datagram structure, but

uses a lower number of user bits. Its function is the addressing of the slave and the transmission of

the desired register address for the read access. The TMC2209 responds with the same baud rate as

the master uses for the read request.

In order to ensure a clean bus transition from the master to the slave, the TMC2209 does not

immediately send the reply to a read access, but it uses a programmable delay time after which the

first reply byte becomes sent following a read request. This delay time can be set in multiples of

eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the

master.

UART READ ACCESS REPLY DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

0 ...... 63

sync + reserved

8 bit master

address

RW + 7 bit

32 bit data

CRC

0…7

8…15

16…23

24…55

56…63

reserved (0)

0xFF

address

data bytes 3, 2, 1, 0

(high to low byte)

CRC

…

The read response is sent to the master using address code %11111111. The transmitter becomes

switched inactive four bit times after the last bit is sent.

Address %11111111 is reserved for read access replies going to the master.

TMC2209 DATASHEET (Rev. 1.03 / 2019-JUN-26) 17

www.trinamic.com

4.2 CRC Calculation

An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to

eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,

including the sync- and addressing byte. The sync nibble is assumed to always be correct. The

TMC2209 responds only to correctly transmitted datagrams containing its own slave address. It

increases its datagram counter for each correctly received write access datagram.

𝐶𝑅𝐶=𝑥

+𝑥

SERIAL CALCULATION EXAMPLE

CRC = (CRC << 1) OR (CRC.7 XOR CRC.1 XOR CRC.0 XOR [new incoming bit])

C-CODE EXAMPLE FOR CRC CALCULATION

void swuart_calcCRC(UCHAR* datagram, UCHAR datagramLength)

{

int i,j;

UCHAR* crc = datagram + (datagramLength-1); // CRC located in last byte of message

UCHAR currentByte;

*crc = 0;

for (i=0; i<(datagramLength-1); i++) { // Execute for all bytes of a message

currentByte = datagram[i]; // Retrieve a byte to be sent from Array

for (j=0; j<8; j++) {

if ((*crc >> 7) ^ (currentByte&0x01)) // update CRC based result of XOR operation

{

*crc = (*crc << 1) ^ 0x07;

}

else

{

*crc = (*crc << 1);

}

currentByte = currentByte >> 1;

} // for CRC bit

} // for message byte

}

4.3 UART Signals

The UART interface on the TMC2209 uses a single bi-direction pin:

UART INTERFACE SIGNAL

PDN_UART

Non-inverted data input and output. I/O with Schmitt Trigger and VCC_IO level.

MS1_ADDR0

IC UART address bit 0 (LSB)

MS2_ADDR1

IC UART address bit 1

The IC checks PDN_UART for correctly received datagrams with its own address continuously. It adapts

to the baud rate based on the sync nibble, as described before. In case of a read access, it switches

on its output drivers and sends its response using the same baud rate. The output becomes switched

off four bit times after transfer of the last stop bit.

Master CPU

(µC with UART)

TMC22xx

different address

(R/W access)

PDN_UART

TXD

RXD

Master CPU

(µC with UART)

TMC22xx #1

same address

(write only access)

PDN_UART

TXD

TMC22xx #2

same address

(write only access)

PDN_UART

TMC22xx

different address

(R/W access)

PDN_UART

MS2_AD1

MS1_AD0

MS2_AD1

MS1_AD0

CCIO

Figure 4.1 Attaching the TMC2209 to a microcontroller UART

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