DW1000用户手册：UWB transceiver的使用与配置

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"DW1000用户手册2.02版" 该文档是DecaWave Ltd在2014年发布的DW1000超宽带(UWB)收发器的用户手册，版本2.02，包含了从如何使用、配置到编程DW1000的详细指导。手册共215页，旨在帮助用户全面了解和操作DW1000设备。 1. **DW1000简介** DW1000是DecaWave设计的一种UWB无线通信芯片，它提供精确的远距离无线定位和高速数据传输功能。此部分介绍了DW1000的基本特性，并简述了手册的目的和结构。 2. **DW1000概述** - **介绍**: 这一部分详细介绍了DW1000的功能和应用场景，以及如何与外部系统接口。 - **接口**: DW1000通常通过SPI（串行外设接口）与微控制器通信，支持多种模式如主机或从机模式，允许灵活的系统集成。 - **操作状态**: 描述了DW1000的不同工作状态，如接收、发送、休眠等。 - **上电复位(POR)**: 解释了设备上电后的初始化过程和默认配置。 - **默认配置**: 详述了设备开机时的预设设置，包括频率、频道、传输功率等。 3. **消息传输** - **基本传输**: 说明了如何进行标准的数据帧传输。 - **传输时间戳**: 提供了关于如何在数据包中添加时间戳以实现高精度时间同步的信息。 - **延迟传输**: 介绍如何设置延迟发送，以便在特定时间点发送数据。 - **扩展长度数据帧**: 描述了支持更大数据量传输的机制。 - **高速传输**: 讨论了DW1000在高速模式下的数据传输能力。 4. **消息接收** - **基本接收**: 阐述了常规的数据接收流程。 - **延迟接收**: 如何实现接收端的时间同步和延迟接收功能。 - **双接收缓冲**: 说明了DW1000如何处理并存储连续的接收数据。 - **低功耗监听模式**: 介绍了设备如何在保持低功耗的同时监听网络活动。 - **低功耗嗅探模式**: 一种进一步降低功耗的接收模式。 - **诊断**: 提供了监控和评估设备性能的工具和方法。 - **评估接收质量和RX时间戳**: 教程如何分析接收到的数据质量以及时间同步的准确性。 5. **媒体访问控制(MAC)硬件特性** - **循环冗余检查(CRC)**: 用于检测数据帧的错误，确保传输的可靠性。 - **帧过滤**: 通过MAC层过滤功能，可以筛选和忽略不符合特定条件的帧。 - **自动帧计数**: 自动计数功能帮助跟踪和管理网络中的数据帧传输。手册的其余部分可能涵盖了更多高级特性和应用示例，包括错误处理、电源管理、射频(RF)参数调整、抗干扰策略、系统级集成以及具体的编程接口等。这个手册对于任何想要利用DW1000芯片构建UWB通信系统的开发者来说都是宝贵的参考资料。

DW1000 User Manual

Version 2.02

Page 16 of 215

State Name

State Description

DEEPSLEEP

With the exception of the OFF state, the DEEPSLEEP state is the lowest power state of

the device.

In DEEPSLEEP all internal circuitry is powered down with the exception of the always-on

memory which can be used to hold the device configuration for restoration on wakeup

Once in DEEPSLEEP the DW1000 remains there until the occurrence of a wakeup event.

This can be either:

1. the SPICSn line pulled low or

2. the WAKEUP line driven high

for the duration quoted in the DW1000 data sheet (nominally 500 μs).

It is also recommended to use the SLP2INIT event status bit (in Register file: 0x0F –

System Event Status Register) to drive the IRQ interrupt output line high to confirm the

wake-up.

Once the DW1000 has detected a wakeup event it progresses into the WAKEUP state.

While in DEEPSLEEP power should not be applied to GPIO, SPICLK or SPIMISO pins as this

will cause an increase in leakage current.

TX state

In the TX state the DW1000 actively transmits a frame the contents of the transmit

buffer on the configured RF channel with the configured transmit parameters (PRF, data

rate, preamble code etc.)

Once the frame transmission is complete the DW1000 may enter one of three modes

depending on the programmed configuration.

After the frame transmission is complete the DW1000 will return to the IDLE state

unless the ATXSLP bit is set (in Sub-Register 0x36:04 – PMSC_CTRL1) in which case the

DW1000 will enter the SLEEP or DEEPSLEEP state automatically, (as long as no host

interrupts are pending).

RX state

In the RX state, the DW1000 receiver is active, either hunting for preamble or (once it

has detected preamble) actively receiving preamble searching for SFD, and subsequently

receiving the PHR, decoding it and receiving the data part of the frame. In the RX state,

the RF synthesizer and all RX blocks are active. After an event that ends the reception,

(either a good frame RX, or some error or timeout event that aborts reception) the

DW1000 will return to the IDLE state unless the ARXSLP bit is set (in Sub-Register

0x36:04 – PMSC_CTRL1) in which case the DW1000 will enter the SLEEP or DEEPSLEEP

state automatically (as long as no host interrupts are pending).

SNOOZE

The SNOOZE state is similar to the INIT state except that a counter is running to cause

the DW1000 to automatically go to the RX state (via INIT and IDLE) when the counter

expires. The snooze count times are in units of the raw 19.2 MHz XTI clock rate, (since

the 125 MHz digital PLL clock is not running).

DW1000 User Manual

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2.4 Power On Reset (POR)

When the external power source is applied to the DW1000 for the first time, the internal Power On Reset

(POR) circuit compares the externally applied supply voltage to an internal power-on threshold

(approximately 1.5 V), and once this threshold is passed the crystal oscillator is enabled and the external

device enable pin EXTON is asserted. An internal counter running off the low power oscillator is used to hold

the DW1000 in reset to ensure that the crystal oscillator is stable before it gets used. Once the digital reset is

de-asserted the digital core wakes up and enters the WAKEUP state. From this state it will automatically turn

on the CLKPLL and wait for it to lock before entering the IDLE state.

Figure 9: Timing diagram and power profile for cold start POR

2.4.1 SLEEP and DEEPSLEEP

In the DW1000 very low power DEEPSLEEP state the IC is almost completely powered down except for a

small amount of memory necessary to maintain IC configurations. This is the lowest power mode of the IC

where the power drain is < 100 nA. To wake the IC from DEEPSLEEP requires an external agent to assert the

WAKEUP input line or the external host microprocessor to initiate an SPI transaction to assert the SPICSn

input.

The DW1000 also includes a low power a SLEEP state where the IC can wake itself from sleeping as a result

of the elapsing of a sleep timer that is running from a low-powered ring oscillator internal to the DW1000 IC.

In this SLEEP state the power drain is < 1 µA. The DW1000 may wake from SLEEP state when the sleep timer

elapses. The WAKEUP or SPICSn inputs may also be used to wake the device.

The frequency of the low power oscillator is dependent on process variations within the IC, but is generally

somewhere in between 7,000 and 13,000 Hz. There are facilities within the IC to measure the length of an

LP oscillator cycle, in counts of the IC crystal oscillator divided by two, (i.e. this is 38.4 MHz ÷ 2, or 19.2 MHz).

IDLE

INIT

OFF

WAKEUP

CLKPLL locked

Crystal stable,

RSTn=1

POWERON

VDDBATT

EXTON

XTAL

VDDDIG

RSTn

por

SPI comms

up to 3MHz

SPI comms up

to max SPI frequency

Battery Inserted

VDDBATT switched on

300µs

4ms

5µs

7µs

CLKPLL

Lock

CLKPLL

enabled

SPI comms not advised

as PLL locks

DW1000 User Manual

Version 2.02

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2.4.1.1 Waking from sleep

The return from SLEEP and DEEPSLEEP modes, is via

 Driving the WAKEUP pin high for approximately 500 μs, (assuming the WAKE_PIN configuration bit is

set in Sub-Register 0x2C:06 – AON_CFG0).

 Driving the SPICSn pin low for approximately 500 μs, (assuming the WAKE_SPI configuration bit is set

in Sub-Register 0x2C:06 – AON_CFG0). This can be achieved by doing a dummy SPI read of sufficient

length.

NOTE: When using the SPICSn pin to wake up the device it is important that the SPIMOSI line is

held low for the duration of the SPICSn to ensure that a spurious write operation does not occur.

In addition return from SLEEP also occurs when

 The internal sleep timer counter expires, (assuming the WAKE_CNT configuration is bit is set in Sub-

In all of three wakeup cases the device is returned to the IDLE state by default but additional state

transitions can be automatically enacted thereafter depending on configurations.

2.4.1.2 Configuration register perseveration

Prior to entering the SLEEP and DEEPSLEEP states and prior to exiting the WAKEUP state, the main DW1000

configurations are copied to and from an Always-On memory (AON). Power is maintained to AON memory

at all times, even in SLEEP and DEEPSLEEP states. The copying of configuration data (saving or restoring)

takes about 7 µs to complete. The detail of which configurations are saved and restored is given in Table

42: Configurations maintained in the AON. Restoration of configurations during the WAKEUP state is only

done if the ONW_LDC configuration bit is set in7.2.45.1 – Sub-Register 0x2C:00 – AON_WCFG.

NB: The host system should avoid SPI access to general system registers or OTP Memory during the

copying period to prevent any conflicts occurring. Access to the TX (or RX) buffer is not restricted during this

period.

2.4.2 Specific state sequences supported by the DW1000

The DW1000 supports a number of state sequences intended to minimize power consumption in certain

applications. These are: -

Mode Name

Mode Description

SNIFF MODE

In SNIFF mode the DW1000 alternates between the RX (on) and the IDLE (off) states.

Further details on this mode are given in section 4.5.1 - SNIFF.

DW1000 User Manual

Version 2.02

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Mode Name

Mode Description

LOW DUTY

CYCLE SNIFF

MODE

In Low duty-cycle SNIFF mode, where the off time is larger, the DW1000 can be

configured to spend this off time in the INIT state which is lower power than the IDLE

state (used for the off period of a SNIFF). Further details of this mode are given in

section 4.5.2 - Low duty-cycle SNIFF.

LOW POWER

LISTENING

Low-Power Listening mode is a special mode where the receiver spends most its time in

a low power (SLEEP or DEEPSLEEP) state only waking up occasionally to sample the air

for a message. This feature is described in detail in section 4.4 - Low-Power Listening

2.5 Default Configuration on Power Up

DW1000 is a highly configurable transceiver with many features. The register reset values have been

selected with the intention of minimising user configuration required. The default configuration may be

summarised as being channel 5, preamble code 4 and mode 2. Channel numbers and preamble codes are as

specified in the standard, IEEE 802.15.4-2011 [1] and mode 2 is as specified in the DW1000 data sheet

modes and comprises the following configurations:

Table 2: Mode 2 Excerpt from DW1000 Data Sheet Operational Modes Table

Mode

Data Rate

PRF

(MHz)

Preamble

(Symbols)

Data

Length

(Bytes)

Packet

Duration (µs)

Typical Use Case

(Refer to DW1000 user manual for further information)

Mode 2

6.8 Mbps

128

152

RTLS, TDOA Scheme, Short Range, High Density

Some further details are given below on the specifics of the default device configuration. For full details the

reader may refer to the register map where the default value of each register is given, section 7 – The

DW1000 register set.

2.5.1 Default System Configuration

Much of the system configuration is configured in the SYS_CFG register, please see section Register file: 0x04

– System Configuration for a full description of the register contents and defaults.

By default, interrupt polarity is active high and all interrupts are disabled, see the SYS_CFG register for

interrupt polarity and the SYS_MASK and SYS_STATUS registers for interrupt configuration and information,

see sections Register file: 0x0E – System Event Mask Register and Register file: 0x0F – System Event Status

GPIOs are set to mode 0, their default function as shown in Table 3.

Table 3: GPIO Default Functions

GPIO Pin

Default Function

GPIO0/RXOKLED

GPIO0

DW1000 User Manual

Version 2.02

Page 20 of 215

GPIO Pin

Default Function

GPIO1/SFDLED

GPIO1

GPIO2/RXLED

GPIO2

GPIO3/TXLED

GPIO3

GPIO4/EXTPA

GPIO4

GPIO5/EXTTXE/SPIPHA

GPIO5

GPIO6/EXTRXE/SPIPOL

GPIO6

SYNC/GPIO7

SYNC

IRQ/GPIO8

IRQ

Smart TX power is on by default, see section Register file: 0x1E – Transmit Power Control and Smart Transmit

Power Control for configuration and operation information.

Sniff mode is off, see Register file: 0x1D – SNIFF Modefor details, frame wait timeout (see SYS_CFG register

bit RXWTOE and Register file: 0x0C – Receive Frame Wait Timeout Period) and preamble detection timeout

(see Sub-Register 0x27:24 – DRX_PRETOC) are off, whilst SFD detection timeout (see Sub-Register 0x27:20 –

DRX_SFDTOC) is on.

Other SYS_CFG register settings such as Automatic Receiver Re-Enable (RXAUTR) and MAC functions such as

frame filtering (FFEN), double buffering (DIS_DRXB) and automatic acknowledgement (AUTOACK) are all off

by default. Automatic CRC generation is on and the CRC LFSR is intialised to 0’s (FCS_INIT2F).

Note that CRC generation is selected as part of a transmit command, see Register file: 0x0D – System Control

External synchronisation and the use of external power amplifiers are deactivated by default, see sections

6.1 – External Synchronisation and 6.2 – External Power Amplification.

2.5.2 Default Channel Configuration

Channel 5, preamble code 4 and 16 MHz PRF are set by default in the CHAN_CTRL register, see Register file:

0x1F – Channel Control for more information.

The transmit data rate is set to 6.8 Mbps in the TX_FCTRL register, see TXBR field in Register file: 0x08 –

Transmit Frame Control . The receive data rate is never set unless 110 kbps reception is required. Note that

this must be configured in register SYS_CFG, field RXM110K, see Register file: 0x04 – System Configuration.

The RF PLL and Clock PLL are configured for channel 5 operation by default, please refer to Register file: 0x2B

– Frequency synthesiser control block for channel configuration settings for each channel.

2.5.3 Default Transmitter Configuration

Transmit RF channel configurations are set for channel 5 by default – see Sub-Register 0x28:0C– RF_TXCTRL.

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