Hynix H9TA4GH2GDMCPR 4GB eMMC+LPDDR2内存芯片规格概览

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Hynix H9TA4GH2GDMCPR是一款整合了4GB NAND闪存（256MB x 16）和2GB LPDDR2-S4B内存（64MB x 32）的多芯片组件(MCP)。该产品旨在提供高效能存储解决方案，适用于需要大容量存储和快速数据传输的应用场景。此文档是一份初步的产品规格说明书，版本为Rev0.3，发布于2012年11月。其中包含了以下关键信息： 1. 操作温度范围：H9TA4GH2GDMCPR支持在极端的温度条件下工作，即-30°C至85°C，确保了产品的可靠性和广泛的环境适应性。 2. 封装形式：采用162球FBGA封装，尺寸为11.5x13.0mm²，具有1.0t厚度和0.5mm间距，这是一种小型化且低引脚数的设计，有助于减小电路板占用空间，并符合环保标准，不含有铅和卤素。 3. 接口兼容性：NAND闪存部分采用开放型NAND闪存接口(ONFI) 1.0标准，这是一种广泛接受的接口规范，方便与其他系统进行无缝集成。 4. 电源电压：产品需要1.0VCC/VCCQ供电，这是为了确保内存和闪存模块在正常工作时所需的电压要求。 5. 规格更改历史：这份规格说明书从初始草稿到0.3版本进行了多次修订，包括阵列组织的修正、编辑错误的调整和表格内容的更新，反映了Hynix对产品性能的持续优化。 6. 功能特性：MCP设计旨在提供高效能，通过将高速的LPDDR2-S4B内存与大容量NAND闪存结合，满足了对存储性能和容量的双重需求。 7. 警告与责任声明：文档明确指出，Hynix不对使用所述电路的任何责任负责，并且没有包含任何专利授权，用户应自行评估设计的适用性和合法性。 H9TA4GH2GDMCPR是Hynix推出的一款高性价比的存储解决方案，其独特的硬件组合、严格的规格管理和持续的规格更新，使之成为工业和个人设备中理想的存储选择。对于系统设计师和工程师来说，理解并遵循这份规格说明书对于正确地集成和利用这款产品至关重要。

Preliminary

H9TA4GH2GDMCPR

NAND 4Gb(x16) / LPDDR2-S4B 2Gb(x32)

Rev 0.3 / Nov. 2012 16

2. BUS OPERATION

There are six standard bus operations that control the device. These are Command Input, Address Input,

Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5ns on Chip Enable, Write

Enable and Read Enable are ignored by the memory and do not affect bus operations.

2.1. Command Input

Command Input bus operation is used to give a command to the memory device. Command are accepted

with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and

latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/

erase) the Write Protect pin must be high. See Figure 4 and “5.9. AC Timing Characteristics" for details of

the timings requirements.

2.2. Address Input

Address Input bus operation allows the insertion of the memory address. 5 clock cycles are needed to

input the addresses. (refer to “1.5. Addressing”). Addresses are accepted with Chip Enable low, Address

Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of

Write Enable. Moreover for commands that starts a modify operation(write/erase) the Write Protect pin

must be high. See Figure 5 and “5.9. AC Timing Characteristics” for details of the timings requirements.

2.3. Data Input

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is

serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch

Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the ris-

ing edge of Write Enable. See Figure 6 and “5.9. AC Timing Characteristics" for details of the timings

requirements.

2.4. Data Output

Data Output bus operation allows to read data from the memory array and to check the status register

content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable

low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 7 to Fig-

ure 9 and “5.9. AC Timing Characteristics" for details of the timings requirements.

2.5. Write Protect

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify opera-

tion do not start and the content of the memory is not altered. Write Protect pin is not latched by Write

Enable to ensure the protection even during the power up.

2.6. Standby

In Standby the device is deselected, outputs are disabled and Power Consumption is reduced.

Preliminary

H9TA4GH2GDMCPR

NAND 4Gb(x16) / LPDDR2-S4B 2Gb(x32)

Rev 0.3 / Nov. 2012 17

3. Device Operation

3.1. Page Read

This operation is initiated by writing 00h and 30h to the command register along with five address cycles.

Two types of operations are available: random read, serial page read. The random read mode is enabled

when the page address is changed. The 1088 (x16) of data within the selected page are transferred to the

data registers in less than 30us(tR). The system controller may detect the completion of this data transfer

(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may

be read out in 45nsec (1.8V version) cycle time by sequentially pulsing RE#. The repetitive high to low

transitions of the RE# clock make the device output the data starting from the selected column address up

to the last column address.

The device may output random data in a page instead of the sequential data by writing random data

output command. The column address of next data, which is going to be out, may be changed to the

address which follows random data output command.

Random data output can be operated multiple times regardless of how many times it is done in a page.

After power up device is in read mode, so 00h command cycle is not necessary to start a read operation.

Any operation other than read or random data output causes device to exit read mode.

Check Figure 10 to Figure 12 as references.reduced.

3.2. Page Program

A page program cycle consists of a serial data loading period in which up to 2176 bytes of data may be

loaded into the data register, followed by a non-volatile programming period where the loaded data is

programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data

Input command (80h), followed by the five cycle address inputs and then serial data. The words other

than those to be programmed do not need to be loaded. The device supports random data input within a

page. The column address of next data, which will be entered, may be changed to the address which

follows random data input command (85h). Random data input may be operated multiple times regardless

of how many times it is done in a page.

The Page Program confirm command (10h) initiates the programming process. The internal write state

controller

automatically executes the algorithms and controls timings necessary for program and verify, thereby

freeing the system controller for other tasks. Once the program process starts, the Read Status Register

commands (70h or 78h) may be issued to read the status register. The system controller can detect the

completion of a program cycle by monitoring the RB# output, or the Status bit (I/O 6) of the Status

in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The

internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The

command register remains in Read Status command mode until another valid command is written to the

command register. Figure 15 to Figure 17 detail the sequence. The device is programmed basically by

page, but it also allows multiple partial page programming of a word or consecutive bytes up to 1088 (x16)

Preliminary

H9TA4GH2GDMCPR

NAND 4Gb(x16) / LPDDR2-S4B 2Gb(x32)

Rev 0.3 / Nov. 2012 18

in a single page program cycle.

The number of consecutive partial page programming operations (NOP) within the same page must not

exceed 4. for example, 2 times for main array (1time/512byte) and 2 times for spare array (1time/16byte).

3.3. Page Re-program

This command allows the re-programming of the same pattern of the last (failed) page into another

memory location. The command sequence initiates with re-program setup (8Bh), followed by the five cycle

address inputs of the target page. If the target pattern for the destination page is not changed compared

to the last page, the program confirm can be issued (10h) without any data input cycle. On the other

hand, if the pattern bound for the target page is different from that of the previous page, data in cycles

can be issued before program confirm “10h”

The device supports random data input within a page. The column address of next data, which will be

entered, may be changed to the address which follows random data input command (85h). Random data

input may be operated multiple times regardless of how many times it is done in a page.

The “program confirm” command (10h) initiates the re-programming process.

The internal write state controller automatically executes the algorithms and controls timings necessary for

program and verify, thereby freeing the system controller for other tasks. Once the program process starts,

the Read Status Register command may be issued to read the status register. The system controller can

detect the completion of a program cycle by monitoring the RB# output, or the Status bit (I/O 6) of the

Status Register. Only the Read Status command and Reset command are valid during programming is in

progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal

write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

3.4. Multiple plane program

Device supports multiple plane program: it is possible to program 2 pages in parallel, one per each plane.

A multiple plane program cycle consists of a double serial data loading period in which up to 4352bytes of

data may be loaded into the data register, followed by a non-volatile programming period where the

loaded data is programmed into the appropriate cell. The serial data loading period begins with inputting

the Serial Data Input command (80h), followed by the five cycle address inputs and serial data for the 1st

page. Address for this page must be in the 1st plane(A17=0 for x16 devices). The device supports random

data input exactly same as in the case of page program operation. The Dummy Page Program Confirm

command (11h) stops 1st page data input and devices becomes busy for a short time (tDBSY).

Once it has become ready again, either the traditional "81h" or the ONFI 1.0 "80h" command must be

issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be in

the 2nd plane (A17=1 for x16 devices).Program Confirm command (10h) makes parallel programming of

both pages to start. Figure 22 and Figure 23 describe the sequences.

User can check operation status by monitoring RB# pin or reading status register commands (70h or 78h),

Preliminary

H9TA4GH2GDMCPR

NAND 4Gb(x16) / LPDDR2-S4B 2Gb(x32)

Rev 0.3 / Nov. 2012 19

as if it were a normal page program: read status register command is also available during Dummy Busy

time (tDBSY).

In case of fail in any of 1st and 2nd page program, fail bit of status register will be set however, in order to

know which page failed, ONFI 1.0 "read status enhanced" command must be issued Refer to section

3.10 for further info.

The number of consecutive partial page programming operations (NOP) within the same page must not

exceed 4. for example, 2 times for main array (1time/512byte) and 2 times for spare array (1time/16byte).

3.5. Block Erase

The Block Erase operation is done on a block basis. Block address loading is accomplished in 3 cycles

initiated by an Erase Setup command (60h). Only addresses A18 to A29 are valid while A12 to A17 are

ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal

erasing process. This two-step sequence of setup followed by execution command ensures that memory

contents are not accidentally erased due to external noise conditions. At the rising edge of WE# after the

erase confirm command input, the internal write controller handles erase and erase-verify. Once the erase

process starts, the Read Status Register commands (70h or 78h) may be issued to read the status register.

The system controller can detect the completion of an erase by monitoring the RB# output, or the Status

bit (I/O 6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are

valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may

be checked.

3.6. Multiple plane Block Erase

Multiple plane erase, allows parallel erase of two blocks in parallel, one per each memory plane.

Two different command sequences are allowed in these case, traditional and ONFI 1.0.

In traditional case, Block erase setup command (60h) must be repeated two times, followed by 1st and

2nd block address respectively (3 cycles each). As for block erase, D0h command makes embedded

operation to start.

In this case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion.

See Figure 24 for details.

As an alternative, the ONFI 1.0 multiplane command protocol can be used, with 60h erase setup followed

by 1st block address and D1h first confirm, 60h erase setup followed by 2nd block address and D0h

(multiplane confirm). Between the two block-related sequences, a short busy time tIEBSY will occur. See

Section 5.8 and Figure 25 for details.

Address limitation required for multiple plane program applies also to multiple plane erase. Also operation

progress can be checked like in the multiple plane program through Read Status Register, or ONFI 1.0

Read Status Enhanced.

As for multiplane page program, the address of the first second page must be within the first plane

(A17=0 for x16 devices) and second plane (A17=1 for x16 devices), respectively.

Preliminary

H9TA4GH2GDMCPR

NAND 4Gb(x16) / LPDDR2-S4B 2Gb(x32)

Rev 0.3 / Nov. 2012 20

3.7. Copy-Back Program

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without

utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are

removed, the system performance is improved. The benefit is especially obvious when a portion of a block

is updated and the rest of the block is also needed to be copied to the newly assigned free block. The

operation for performing a copy-back program is a sequential execution of page-read without serial access

and copying-program with the address of destination page. A read operation with "35h" command and the

address of the source page moves the whole 1088 words(x16 Device) data into the internal data buffer. As

soon as the device returns to Ready state, optional data read-out is allowed by toggling RE#, or Copy Back

command (85h) with the address cycles of destination page may be written. The Program Confirm

command (10h) is required to actually begin the programming operation. Data input cycle for modifying a

portion or multiple distant portions of the source page is allowed as shown in Figure 18 "Copy Back

Program with Random Data Input". "When there is a program-failure at Copy-Back operation, error is

reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to

charge loss is not checked by external error detection/correction scheme. For this reason, four bit error

correction is recommended for the use of Copy-Back operation. Figure 18 shows the command sequence

for the copy-back operation. Please note that there are two things to do during copy-back program. First,

Random Data Input (with/without data) is entered before Program Confirm command(10h) after Random

Data output. Second, WP# value is don't care during Read for copy back, while it must be set to Vcc When

performing the program.

3.8. Multiple plane copy back Program

As for page program, device supports Multi-plane copy back program with exactly same sequence and

limitations. Multiplane copy back program must be preceded by 2 single page read for copy back command

sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane).

Multi-plane copy back cannot cross plane boundaries : the contents of the source page of one device plane

can be copied only to a destination page of the same plane.

Also in this case, two different sequences are allowed : the traditional one (85h, first plane address 11h,

81h, second plane address, 10h) represented in Figure 26, and ONFI 1.0 sequence (85h, first plane

address 11h, 85h, second plane address, 10h) represented in Figure 27 and Figure 29.

3.9. Special read for copy back

The device feature the "special read for copy back".

If copy back read (described in sections 3.7 and 3.8) is triggered with confirm command "36h" instead

"35h", copyback read from target page(s) will be executed with an increased internal (Vpass) voltage.

This special feature is used in order to try to recover incorrigible ECC read errors due to over-program or

read disturb: it shall be used ONLY if ECC read errors have occurred in the source page using "standard

read" or "standard read for copy back" sequences.

Excluding the copy-back read confirm command, all other features described in sections 3.7 and 3.8 for

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