CIC滤波器在多标准接收器中的低功耗设计与应用

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本文档深入探讨了在多标准无线通信接收器中应用CIC滤波器的设计与实现，特别是在高采样率和不同信道带宽需求的情况下。CIC滤波器因其在高倍抽取率场景中的高效性和低复杂性而备受关注。文章首先介绍了CIC滤波器的基本原理，它是一种线性相位、无混叠区域的结构，特别适用于频域滤波和抽取操作。传统的CIC滤波器通常是递归结构，但为了简化设计并降低系统资源消耗，文中提出了一种非递归形式的CIC滤波器。这种转换通过将CIC多项式分解，实现了K级CIC抽取，每级抽取率为2倍。这样的设计使得滤波器的实现更加灵活，尤其在第一级的高倍抽取时，能有效减少电路复杂度和功耗。针对GSM和DECT等通信标准的应用，文档着重介绍了一种低功耗的五阶组合抽样滤波器，支持可编程的下采样比率（16和8）以及相应的采样率（12.8MHz和44.8MHz）。非递归架构的优势在于减少了反馈路径，从而降低了环路噪声和信号失真，提高了整体系统的性能和稳定性。此外，文中还探讨了低功率VLSI（Very Large Scale Integration）实现技术，这些技术包括优化的电路设计、高效的数字信号处理算法以及电源管理策略，旨在减小器件尺寸，降低能耗，满足现代无线通信设备对小型化和节能的需求。总结来说，本文研究的CIC滤波器设计方法不仅提升了多标准无线通信接收器的性能适应性，而且通过非递归结构和多相抽取技术，显著地优化了系统资源使用和功耗控制，是当前无线通信领域中一个重要的研究方向。对于从事射频通信设计和信号处理的工程师来说，理解和掌握这类技术对于开发出更高效、低功耗的无线设备具有重要意义。

ABSTRACT

In multi-standard transceivers a programmable

decimation ﬁlter is required to perform channel

select ﬁltering at baseband since the channel

bandwidths, sampling rates, and CNR require-

ments are different. This paper presents a low

power ﬁfth-order comb decimation ﬁlter with

programmable decimation ratios (16 and 8) and

sampling rates (12.8 MHz and 44.8 MHz) for

GSM and DECT applications. The non-recur-

sive architecture for comb ﬁlter is employed and

low power VLSI implementation techniques are

developed.

INTRODUCTION

Recent research on radio frequency (RF) com-

munication transceivers focuses on both higher

integration and multi-standard operation. High-

er integration can be obtained by optimizing re-

ceiver architectures to eliminate the off-chip

components. The receiver architectures that per-

forms channel select filtering on chip at base-

band are preferred since digital signal

processing techniques can be easily applied to

adapt to multiple communication standards. Fig.

1 shows the wide-band intermediate frequency

with double conversion (WIF) architecture [1]

which can be used to implement a multi-stand-

ard (DECT and GSM) receiver. The WIF archi-

tecture needs a high dynamic range

oversampling sigma-delta (SD) analog-to-digit-

al (A/D) converter that can adapt to the different

requirements from the multi-standards. The dy-

namic range of a SD A/D converter can be easily

adjusted by selecting different oversampling ra-

tios. Therefore a decimation filter with program-

mable decimation ratios is needed in the A/D

converter.

While the sampling rate and resolution of

oversampling SD A/D converters are typically

determined by their analog modulators, the

power consumption is governed largely by the

digital decimation filters [2]. It is possible to at-

tenuate the quantization noise and undesired

channels with a single filter and then decimate to

the Nyquist rate, but this approach consumes

much power. By decimating in multiple stages,

the complexity of the filters is reduced, and sub-

sequent filters operate at lower sampling rates,

further reducing the power consumption [3]. In

multi-stage decimation filters it has been shown

in [4] that the comb filter is an efficient way to

decimate the output of the analog modulator to

four times the Nyquist rate. Fig. 2 shows a multi-

stage decimation filter suitable for GSM and

DECT applications. To meet the system require-

ments, a ﬁfth-order comb decimation ﬁlter (6-bit

input) with programmable decimation ratios

16(GSM) / 8(DECT), and sampling rates 12.8

MHz(GSM) / 44.8 MHz(DECT) is needed.

Since the comb filter operates at the high sam-

pling rate its power consumption is large. Hence

low power implementation of the comb filter is

very important.

The non-recursive architecture [5] for comb

ﬁlters has lower power consumption compared

with Hogenauer’s cascaded-integrator-comb

(CIC) architecture [3] especially when the ﬁlter

orders and decimation ratios are high. In this

paper the non-recursive architecture is

employed to design the comb ﬁlter. Low power

techniques have been developed for VLSI

implementation of the non-recursive architec-

ture.

Low-Power Implementation of a Fifth-Order Comb Decimation Filter for

Multi-Standard Transceiver Applications

Yonghong Gao and Hannu Tenhunen

Electronic System Design Laboratory, Royal Institute of Technology

Electrum 229, Isafjordsgatan 22, SE-164 40 Kista, Stockholm, Sweden

gaoyh@ele.kth.se

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