TI TLC6C5712-Q1：8通道LED驱动器，AEC-Q100兼容

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TI-TLC6C5712-Q1是一款专为汽车电子应用设计的高性能集成驱动器，它具备8通道的全桥LED驱动能力，符合AEC-Q100标准，确保了在严苛的汽车环境中稳定运行。这款器件的特点主要体现在以下几个方面： 1. 供电及电流控制：该产品支持3-V to 5.5-V的宽电压输入范围，可以驱动LED负载。每个通道的最大恒定电流高达75mA，通过外部电阻进行编程，允许用户根据需求调整电流输出。同时，它具有出色的电流精度，即使在不同通道或设备间，电流偏差也能保持在小于±3%的范围内。 2. 电压管理：最高输出电压可达7V，且在不同负载电流下，压降电压有所优化，如50mA时每个通道的压降为0.75V，75mA时为1.2V。这对于保持LED的高效工作至关重要。 3. PWM功能：TLC6C5712-Q1支持6个带频率监控的PWM输入，提供了灵活的外部脉宽调制，可用于实现精细的亮度控制。通过SPI接口，可以实现通道映射的编程，便于系统级的信号处理和控制。 4. 保护与诊断：器件内置保护机制，包括对短路、开路负载以及误连接（如将输出短接到地）的检测，确保了系统的安全性和可靠性。此外，在激活和禁用状态下，它还能检测电路状态，便于故障排查。 5. 安全与认证：符合AEC-Q100标准，针对汽车应用的严格要求，其器件温度等级为1，适用于-40°C至125°C的工作环境，并通过ESD（静电放电）分类等级H3A和CDM等级C4B，确保在高电压和静电环境下也能正常运作。 6. 可靠性与支持：最后，数据手册中还包含生产数据、技术文档、工具软件、支持服务和社区资源等，为用户提供全面的产品支持和解决方案。 TLC6C5712-Q1是一款性能强大、稳定性高的LED驱动芯片，适用于汽车照明、仪表盘指示等应用，它的特性使得设计师能够轻松实现精确控制和保护，确保系统的可靠性和效能。

POR_ERROR_FLAG

POR_MASK

ERR

Other Faults

Start-Up and

UVLO POR

SOFTWARE_POR

TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

www.ti.com.cn

7.3 Feature Description

7.3.1 Power-On Reset (POR)

The device supports two types of POR, start-up or UVLO POR and software POR, with software reset capability.

7.3.1.1 Start-Up or UVLO POR

When power is applied to V

, or when V

is undervoltage (V

< V

(POR)

), an internal power-on reset (POR)

holds the TLC6C5712-Q1 device in a reset condition with the following conditions until V

reaches VPOR.

During RESET:

• The device cannot receive data.

• The SDO pin is held LOW, so the device cannot transmit data.

• The ERR open-drain output is pulled down.

During POR, communication between the controller and the device is lost. Any data transmitted during this

period is lost. The state machine inside the device is undefined. After POR, the reset status is released, the

TLC6C5712-Q1 registers and SPI state machine are re-initialized to default states (see the Default column in 表

2). [POR_ERR_FLAG] is set to HIGH during start-up or UVLO POR.

7.3.1.2 Software POR

A software reset command (<SOFTWARE_POR>) resets all internal register settings to default values. The

command executes on a LATCH rising edge. All fault bits and diagnostic status are cleared and set to their

default values. The <SOFTWARE_POR> command also executes the RESET_STATUS] command. The

[POR_ERR_FLAG] bit in the <READ_STATUS0> register is set to HIGH on a software POR.

7.3.1.3 Reset POR

Either start-up or a UVLO POR or a software POR sets [POR_ERR_FLAG] to HIGH. when the device enters

POR status, the [POR_ERR_FLAG] bit is latched HIGH. To clear the [POR_ERR_FLAG], a RESET_POR

command must be issued.

If [POR_ERR_FLAG] is set either by start-up, UVLO, or software, and the device is not in any UVLO state,

[POR_ERR_FLAG] is latched and does not block any operation.

7.3.1.4 POR Masking

[POR_ERR_FLAG] reporting to the ERR output can be masked by the [POR_MASK] bit. If a POR event happens

when [POR_MASK] is set HIGH, POR events do not trigger the ERR output, and [POR_ERR_FLAG] is set

HIGH.

图图 15. POR Error Report Topology

See the following addresses in 表 2: 61h, 62h, 63h, and A2h.

7.3.2 Error Feedback

The TLC6C5712-Q1 device supports an active-low open-drain output for error information through the ERR pin

for the MCU error-monitor interrupt. If any FLAG bit is set to HIGH in the <READ_STATUS0> register, and is not

masked by a corresponding mask bit in the <WRITE_ERROR_MASK> register, the ERR pin pulls low to indicate

an ERROR scenario. The MCU should immediately execute the error monitor routine.

TLC6C5712-Q1

www.ti.com.cn

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

Feature Description (接接下下页页)

7.3.2.1 Recovery From Error

When any fault occurs, all FAULT information can be read in separate FAULT registers, for example,

<READ_OPEN_FAULT0>. When the error condition recovers, the register information is still latched and the

ERR pin remains low until the fault is masked or the RESET_STATUS command has been issued. However, if

the error condition still exists after issuing the RESET_STATUS command, the ERR pin pulls low again and the

corresponding FAULT register is set HIGH.

7.3.2.2 RESET_STATUS Command

The RESET_STATUS command clears all flags in the following registers:

<READ_ADJSHORT0>

<READ_ADJSHORT1>

<READ_SHORT_FAULT0>

<READ_SHORT_FAULT1>

<READ_SHORT_GND_FAULT0>

<READ_SHORT_GND_FAULT1>

<READ_OPEN_FAULT0>

<READ_OPEN_FAULT1>

<READ_PWM_FAULT>

<READ_STATUS0>, excluding the [POR_ERR_FLAG] bit.

As mentioned in the POR section, only the RESET_POR command can clear the [POR_ERR_FLAG] bit.

[POR_ERR_FLAG] bit: Read only (R) bit. HIGH: A POR error has occurred. To reset this flag, issue a

RESET_POR command.

[POR_MASK] bit: Read and write (R/W) bit. HIGH: A POR error is stored in the [POR_ERR_FLAG] bit

and is not reported to ERR.

RESET_POR: A command to reset [POR_ERR_FLAG].

SOFTWARE_POR: A command to generate a POR. It also clears STATUS flags.

See the following addresses in 表 2: 62h, 9Ah through A2h, A8h, and A9h.

7.3.3 PWM Input

The TLC6C5712-Q1 device has six PWM inputs with independently configurable mapping to modulate any of the

12 channels for external PWM dimming. A PWM monitor can be used to supervise PWM input-signal integrity.

7.3.3.1 PWM Dimming

PWM dimming is supported on all 12 channels by six PWM inputs. The input PWMx signal is active-low. Due to

the minimal pulse duration needed for diagnostics, at 200 Hz the minimum achievable duty cycle is 0.1%, or 5 µs

minimal on-time. Similarly, the maximum achievable duty cycle is 99.2%, or 40 µs minimum off-time. The setting

of this boundary allows enough time for diagnostic functions. In the case of 0% or 100% PWM, diagnostics are

not reported.

7.3.3.2 PWM Monitor

Independent rising-edge triggered timers are implemented as PWM monitors for each PWMx input channel.

when the timer length reaches the threshold t

PWM

, [PWM_FAULTx] is set to HIGH. If the corresponding masking

[ANY_PWM_FAULT_FLAG] register. [ANY_PWM_FAULT_FLAG] is set to HIGH and the ERR pin is pulled LOW

if any of the PWM monitors reported a fault and the mask register [PWM_MASK] is disabled. The PWM rising

edge resets the timer and restarts counting from 0. For 0% or 100% PWM, the [PWM_FAULTx] registers should

be independently masked for each PWMx input via the [PWM_FAULT_MASKx] registers.

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