NIS5135 Series
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V
CC
= 5.0 V, C
L
= 70 mF, dv/dt pin open, R
LIMIT
= 10 W, T
J
= 25°C
unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
POWER FET
Delay Time (enabling of chip to I
D
= 100 mA with 1 A resistive load) T
dly
500
ms
ON Resistance (Note 4)
T
J
= 140°C (Note 5)
R
DSon
54 68
95
82
mW
Off State Output Voltage
(V
CC
= 10 V
dc
, V
GS
= 0 V
dc
, R
L
= R)
V
off
50 200 mV
Output Capacitance
V
DS
= 5 V
DC
, V
GS
= 0 V
DC
, R
L
= R
C
out
230 pF
Continuous Current (T
A
= 25°C, 0.5 in
2
pad) (Note 5)
(T
A
= 80°C, minimum copper)
I
D
I
D
3.6
1.7
A
THERMAL LATCH
Shutdown Temperature (Note 5) T
SD
150 175 200 °C
Thermal Hysteresis (Decrease in die temperature for turn on, does not
apply to latching parts)
T
Hyst
45 °C
UNDER/OVERVOLTAGE PROTECTION
V
OUT
Maximum (V
CC
= 10 V) V
out−clamp
5.95 6.65 7.35 V
Undervoltage Lockout (Turn on, Voltage Going High) V
UVLO
3.2 3.6 4.0 V
UVLO Hysteresis V
Hyst
− 0.40 − V
CURRENT LIMIT
Kelvin Short Circuit Current Limit (R
Limit
= 11 W, Note 6)
I
LIM
2.3 3.1 3.9 A
Kelvin Overload Current Limit (R
Limit
= 11 W, Note 6)
I
LIM
3.5 A
dv/dt Circuit
Output Voltage Ramp Time (Enable to V
OUT
= 4.7 V) t
slew
0.70 1.4 2.4 ms
Maximum Capacitor Voltage V
max
V
CC
V
ENABLE/FAULT
Logic Level Low (Output Disabled) V
in−low
0.35 0.58 0.81 V
Logic Level Mid (Thermal Fault, Output Disabled) V
in−mid
0.82 1.4 1.95 V
Logic Level High (Output Enabled) V
in−high
1.96 2.64 3.30 V
High State Maximum Voltage V
in−max
3.40 4.30 5.2 V
Logic Low Sink Current (V
enable
= 0 V) I
in−low
−12 −20
mA
Logic High Leakage Current for External Switch (V
enable
= 3.3 V) I
in−leak
1.0
mA
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
Fan 3.0 Units
TOTAL DEVICE
Bias Current (Operational) I
Bias
1.5 2.0 mA
Bias Current (Shutdown) I
Bias
1.0 mA
Minimum Operating Voltage (Notes 5 and 7) V
min
3.1 V
4. Pulse test: Pulse width 300 ms, duty cycle 2%.
5. Verified by design.
6. Refer to explanation of short circuit and overload conditions in application note AND8140/D.
7. Device will shut down prior to reaching this level based on actual UVLO trip point.
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