Verilog编程陷阱与标准细节揭秘

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本文档深入探讨了Verilog和SystemVerilog语言中的陷阱与标准细节，这些细节对于工程师来说至关重要。作者Stuart Sutherland和Don Mills，分别来自Sutherland HDL, Inc.和Microchip Technology，聚焦于编程语言中的微妙规则，这些规则有时可能导致程序员在设计和测试过程中无意间引入错误或引发难以预料的问题。标题中的"Standard Gotchas"一词指出了标准规范中可能存在的不易察觉的问题，即"陷阱"，这些陷阱可能因为设计得引人误用而显得诱人，但其行为结果往往出乎意料，从而导致bug或错误。文中引用了关于经典编程陷阱的一个例子，即`if (a = b) { code; }` 的语法虽然合法，但在大多数情况下并非程序员的初衷，他们可能期望的是等价的 `if (a == b) { code; }`，后者只有当a和b相等时才会执行代码。 Verilog和SystemVerilog标准详尽地规定了软件工具解析设计和测试台代码的方式，这包含在IEEE的两个语言参考手册中，总计超过1,500页。文章的目标是揭示这些复杂的规则，并提供实用的建议，帮助工程师们避免常见的设计误区，提高代码质量，确保设计的正确性和一致性。阅读本文将有助于读者理解以下知识点： 1. **语言陷阱识别**：学习如何识别标准中潜在的陷阱，如逻辑赋值与比较运算符的差异。 2. **规范解读**：掌握IEEE Verilog和SystemVerilog语言规范的细微差别，防止由于误解标准而导致的错误。 3. **代码编写最佳实践**：学习如何编写更清晰、更符合标准的代码，减少意外行为。 4. **工具依赖理解**：理解软件工具如何解析代码，以便在必要时进行调试和优化。 5. **设计文档与沟通**：强调了文档的重要性，特别是在涉及复杂逻辑和行为时，确保团队成员对代码意图有共同的理解。这篇论文提供了宝贵的指导，使工程师能够在设计和开发过程中更加谨慎，从而避免在使用Verilog和SystemVerilog时陷入潜在的陷阱。通过遵循文章中提供的策略和技巧，可以显著提升设计质量和效率。

SNUG Boston 2006 11 Standard Gotchas in Verilog and SystemVerilog

SystemVerilog allows tasks and functions to be defined in $unit, packages, and interfaces. These

tasks and functions can then be called from multiple modules. Any static storage in these tasks

and functions is shared by all places from which the task or function is called.

How to avoid this gotcha: Declare tasks and functions in $unit, packages, or interfaces as

automatic, with no static storage within the task or function. Each call to an automatic task or

function will allocate unique storage for that call, instead of sharing the task/function storage. An

exception to this guideline is a task or function within an interface that is only called from within

the interface.

2.11 Importing enumerated types from packages

Gotcha: Importing an enumerated type does not import the enumerated labels.

Enumerated type definitions defined in a package can be explicitly imported into a design or

verification block. For example:

package chip_types;

typedef enum logic [1:0] {RESET, WAITE, LOAD, READY} states_t;

endpackage

module chip (...);

import chip_types::states_t; // explicit import of states_t type

states_t state, next_state;

always_ff @(posedge clock, posedge reset)

if (reset) state <= RESET; // GOTCHA: RESET has not been imported

else state <= next_state;

...

endmodule

How to avoid this gotcha: This gotcha can usually be avoided by wildcard importing the package.

In this way, both the enumerated type definition and the enumerated labels are imported.

module chip (...);

import chip_types::*; // wildcard import of package declarations

However, wildcard imports have a gotcha if multiple packages are used in a design block, as

discussed in Section 2.12, which follows.

2.12 Importing from multiple packages

Gotcha: Wildcard imports from multiple packages can cause name collisions.

Large designs, and designs that use IP models, will likely divide declarations into multiple

packages. A common modeling style is to wildcard import these packages into a design block, or

into the $unit global declaration space. Wildcard imports are convenient, as they can save

considerable typing over explicitly importing each item from each package. However, wildcard

imports of multiple packages can lead to a gotcha, as illustrated in the following example:

package bus1_types;

parameter SIZE = 32;

...

endpackage

SNUG Boston 2006 13 Standard Gotchas in Verilog and SystemVerilog

if (!rst_n) State <= WAITE;

else State <= NextState;

...

endmodule: chip

In the example above, the always_ff flip-flop in module chip is supposed to reset on a negative

edge of

rst_n. The testbench sets rst_n to zero at the beginning of simulation, and holds it low

for 3 nanoseconds. However, in the testbench,

rst_n is a 2-state type, which begins simulation

with a value of zero. Setting rst_n to zero does not change its value, and therefore does not cause

a negative edge on rst_n. Since the testbench does not cause a negative edge on rst_n, the

always_ff sensitivity list for the flip-flop in module chip does not trigger, and the flip-flop does

not reset asynchronously. If rst_n were held low at least one clock cycle, the flip-flop would

reset synchronously when clock occurred. In this example, though, the test stimulus does not hold

rst_n low a full clock cycle, and therefore the reset is completely missed. GOTCHA!

How to avoid this gotcha: This gotcha can be avoided in a number of ways. One way is to

initialize the 2-state reset signal to the non reset value with a blocking assignment, and then to the

reset value with a nonblocking assignment: This will trigger the always_ff blocks waiting for a

negative edge of reset. Additionally, the nonblocking assignment will ensure that all the

always_ff blocks are active before the transition to zero occurs.

initial begin

rst_n = 1; // initialize to inactive value

rst_n <= 0; // set reset to active value using nonblocking assign

#3ns rst_n = 1;

...

A second way to avoid this gotcha is to ensure that the reset is held longer then a clock period,

thus using the clock to trigger the always_ff block. This is not a recommended approach, due to

reset acting like a synchronous reset, rather than an asynchronous reset, which means that the

RTL simulation does not match the gate-level simulation or the design intent.

A third way to fix this gotcha is to use 4-state types instead of 2-state types for active-low signals.

4-state variable types will begin simulation with a value of X. Assigning a 4-state type a value of

zero, even at simulation time zero, will cause an X to zero transition, which is a negative edge.

Note: VCS version 2006.06 does not fully adhere to the IEEE SystemVerilog standard for 2-state

types. The standard says that 2-state types should begin simulation with a value of zero. In VCS,

2-state variable types automatically transition to zero sometime during simulation time zero. This

will cause a negative edge transition at simulation time zero, which might, depending on event

ordering, trigger the design procedural blocks that are looking for a negative edge transition. This

tool-specific, non-standard behavior can hide this 2-state reset gotcha. Engineers should not rely

on this tool-specific behavior as a solution to the gotcha. It is dependent on event ordering, and, at

some future time, VCS could implement the 2-state behavior as it is specified in the standard.

3.2 Locked state machines

Gotcha: 2-state state machines can lock up in the start-up state.

By default, enumerated types are 2-state types, and the default value of the first label in the

enumerated list is zero. Functional logic based on 2-state enumerated data types can have gotchas.

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