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首页Ublox LEA-6/NEO-6 GPS模块集成手册:高性价比设计指南
本指南深入探讨了Ublox LEA-6和NEO-6系列GPS模块的设计细节,特别针对硬件工程师而言,具有极高的实用价值。Ublox是一家专注于高性价比且性能卓越的GPS模块制造商,其LEA-6和NEO-6模块集成了u-blox 6定位引擎,展现出出色的导航能力。这些模块设计紧凑,易于集成,是独立式GPS接收器的理想选择。 LEA-6和NEO-6模块的特点在于它们的高度灵活性,支持多种电源选项,让设计师在满足不同应用需求的同时,兼顾功耗和成本效益。它们的SMT(表面安装技术)封装使得自动化组装成为可能,无论是标准的拾取和放置机器还是回流焊设备,都能高效完成大规模生产,从而大大缩短产品上市时间。 此外,文档还强调了这些模块在定位、通信和加速方面的功能,旨在帮助用户迅速准确地定位设备位置,并通过内置的AGPS(辅助全球定位系统)增强定位精度,确保在城市峡谷或其他信号较弱地区也能提供稳定的定位服务。值得注意的是,文档中提供的信息基于早期版本,后续可能会有修订和补充内容发布,因此建议读者在实际操作前参考最新的官方资料。 LEA-6/NEO-6 GPS模块设计指南提供了详尽的技术参数、接口规范以及集成指南,对于硬件工程师在项目开发过程中选择和优化GPS解决方案具有重要的参考价值。通过了解和遵循这份手册,硬件工程师可以充分利用Ublox的先进技术,实现高效、可靠的GPS定位应用设计。
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LEA-6 / NEO-6 - Hardware Integration Manual
GPS.G6-HW-09007-A Preliminary Hardware description
Page 11 of 62
The Power Save mode is an autonomous mode that does not require dynamic interaction by the application
engine, i.e. after the configuration settings communicated to the u-blox 6 receiver, the application does not
need to take care of switching off and on the receiver to obtain low power consumption.
With NEO-6G the Power Save Mode does not achieve lowest possible current during backup mode (SW backup
current). This leads to reduced power savings only for the combination of very long off-times (several hours) and
1.8 V supply. For this scenario, better current savings can be achieved if the Module is externally turned off.
Please refer to the u-blox 6 Receiver Description including Protocol Specification [3] for more information. This
document is available on the
ublox website.
Power Save mode is not available with LEA-6R.
1.4 Antenna supply - V_ANT (LEA-6)
LEA-6 modules support active antenna supply and supervision use the pin V_ANT to supply the active antenna.
Use a 10R resistor in front of V_ANT. For more information about antenna and antenna supervisor see chapter
2.5.
1.5 System functions
1.5.1 EXTINT - External interrupt pin
EXTINT0 is an external interrupt pin used for the time mark function on LEA-6T.
It can be used for wake-up functions in Power Save mode on all LEA-6 and NEO-6 modules.
1.5.2 System monitoring
The u-blox-6 receiver modules provide system monitoring functions that allow the operation of the embedded
processor and associated peripherals to be supervised. These System Monitoring functions are output as part of
the UBX protocol, class ‘MON’.
Please refer to the u-blox 6 Receiver Description including Protocol Specification [3]. For more information on
UBX messages, serial interfaces for design analysis and individual system monitoring functions.
1.6 Interfaces
1.6.1 UART
u-blox 6 modules include a Universal Asynchronous Receiver Transmitter (UART) serial interface. RxD1/TxD1
supports data rates from 4.8 to 230.4 kBit/s. The signal output and input levels are 0 V to VCC. An interface
based on RS232 standard levels (+/- 12 V) can be realized using level shifters such as Maxim MAX3232.
Hardware handshake signals and synchronous operation are not supported.
For the default settings see the module data sheet.
1.6.2 USB
The u-blox 6 Universal Serial Bus (USB) interface supports the full-speed data rate of 12 Mbit/s.
1.6.2.1 USB external components
The USB interface requires some external components in order to implement the physical characteristics required
by the USB 2.0 specification. These external components are shown in Figure 4 and listed in Table 1.
In order to comply with USB specifications, VBUS must be connected through a LDO (U1) to pin VDD_USB of
the module.
If the USB device is self-powered it is possible that the power supply (VCC) is shut down and the Baseband-IC
core is not powered. Since VBUS is still available, it still would be signaled to the USB host that the device is
present and ready to communicate. This is not desired and thus the LDO (U1) should be disabled using the
LEA-6 / NEO-6 - Hardware Integration Manual
GPS.G6-HW-09007-A Preliminary Hardware description
Page 12 of 62
enable signal (EN) of the VCC-LDO or the output of a voltage supervisor. Depending on the characteristics of the
LDO (U1) it is recommended to add a pull-down resistor (R11) at its output to ensure VDD_USB is not floating if
LDO (U1) is disabled or the USB cable is not connected i.e. VBUS is not supplied.
If the device is bus-powered, LDO (U1) does not need an enable control.
Module
VDD_USB
LDO
VDD_USB
R4
USB_DP
USB_DM
R5
C24 C23
D2
VBUS
DP
DM
GND
USB Device Connector
U1
EN
R11
EN
Figure 4: USB Interface
Name Component Function Comments
U1 LDO Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V.
Almost no current requirement (~1 mA) if the GPS receiver is operated as a USB
self-powered device, but if bus-powered LDO (U1) must be able to deliver the
maximum current of ~150 mA. A low-cost DC/DC converter such as LTC3410
from Linear Technology may be used as an alternative.
C23,
C24
Capacitors Required according to the specification of LDO U1
D2 Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5 Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44 Ohms
A value of 22 Ohms is recommended.
R11 Resistor 10k R is recommended for USB self-powered setup. For bus-powered setup
R11 can be ignored.
Table 1: Summary of USB external components
1.6.3 Display Data Channel (DDC)
An I
2
C compatible Display Data Channel (DDC) interface is available with LEA-6 and NEO-6 modules for serial
communication. For more information about DDC implementation refer to the u-blox 6 Receiver Description
including Protocol Specification [3]. Background information about the DDC interface is available in Appendix
C.1.
u-blox 6 GPS receivers normally run in I
2
C slave mode. Master Mode is only supported when external
EEPROM is used to store configuration. No other nodes may be connected to the bus. In this case, the
receiver attempts to establish presence of such a non-volatile memory component by writing and reading
from a specific location.
Pins SDA2 and SCL2 have internal 13kOhm pull-ups. If capacitive bus load is very large, additional external pull-
ups may be needed in order to reduce the pull-up resistance.
Table 2 lists the maximum total pull-up resistor values for the DDC interface. For small loads, e.g. if just
connecting to an external EEPROM, these built-in pull-ups are sufficient.
Load Capacitance Pull-Up Resistor Value R20, R21
50 pF N/A
100 pF
18 kΩ
250 pF
4.7 kΩ
Table 2: Pull-up resistor values for DDC interface
LEA-6 / NEO-6 - Hardware Integration Manual
GPS.G6-HW-09007-A Preliminary Hardware description
Page 13 of 62
1.6.3.1 Communicating to an I
2
C EEPROM with the GPS receiver as I
2
C master
Serial I
2
C memory can be connected to the DDC interface. This can be used to save configuration permanently. It
will automatically be recognized by firmware. The memory address must be set to 0b10100000 (0xA0) and the
size fixed to 4 kB.
Figure 5: Connecting external serial I
2
C memory used by the GPS receiver (see EEPROM data sheet for exact pin orientation)
Figure 6: Connecting external serial I
2
C memory used by external host (see data sheet for exact pin orientation)
Note that the case shown on Figure 5 is different than the case when EEPROM is present but used by external
host / CPU as indicated on Figure 6. This is allowed but precaution is required to ensure that the GPS receiver
does not detect the EEPROM device, which would effectively configure the GPS receiver to be MASTER on the
bus causing collision with the external host.
To ensure that the EEPROM device (connected to the bus and used by the host) is not detected by the GPS
receiver it is important to set the EEPROM’s address to a value different than 0xA0. This way EEPROM remains
free to be used for other purposes and the GPS receiver will assume the SLAVE mode.
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