STM32F20x 芯片手册：ARM Cortex-M3 MCU，高速USB,以太网功能

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"STM32F20x的英文版芯片手册，包含了STM32F205xx和STM32F207xx系列微控制器的详细规格和技术特性，适用于开发过程中查阅。" STM32F20x系列是基于ARM Cortex-M3内核的32位微控制器，其主要特点包括高性能、低功耗和丰富的外设接口。以下是该系列芯片的关键技术要点： 1. **核心性能**：采用ARM Cortex-M3处理器，内置自适应实时加速器（ART Accelerator），确保在Flash存储器中实现零等待状态执行，工作频率可达120MHz。它提供了150 DMIPS的处理能力，对应于Dhrystone 2.1基准测试下的1.25 DMIPS/MHz。 2. **内存配置**：提供最大1MB的闪存（Flash）存储空间，用于存储程序代码；512字节的只读一次可编程存储器（OTP）；最高128+4KB的静态随机访问存储器（SRAM），满足高速数据处理需求。此外，灵活的静态存储器控制器支持CompactFlash、SRAM、PSRAM、NOR和NAND等不同类型的外部存储器。 3. **显示接口**：具备LCD并行接口，支持8080和6800模式，可以连接各种液晶显示屏。 4. **时钟、复位和电源管理**：工作电压范围为1.65V到3.6V，具有上电复位（POR）、掉电复位（PDR）、电源电压检测（PVD）和过压保护（BOR）。支持4到26MHz的晶体振荡器，内置16MHz的工厂校准RC振荡器（25°C时精度为1%），以及32kHz的RTC校准振荡器和内部32kHz RC振荡器。 5. **低功耗模式**：包含睡眠、停止和待机三种低功耗模式，以及VBAT电源，用于RTC、20个32位备份寄存器和可选的4KB备份SRAM，保证在低功耗状态下也能维持部分功能运行。 6. **模拟转换器**：集成了3个12位的模数转换器（ADC），转换速度最快可达0.5μs，最多可连接24个通道，支持多种模拟信号输入。 7. **通信接口**：提供了多达15种通信接口，包括USB OTG高速/全速、以太网、多个定时器（TIMs）以及3个模数转换器和1个数模转换器，适配多种外设连接需求。 8. **其他特性**：还包含了温度传感器、多种定时器、看门狗定时器、GPIO引脚等多种功能，为复杂系统设计提供了全面的支持。 STM32F20x系列微控制器因其高性能、广泛的外设支持和灵活性，在嵌入式系统、物联网设备、工业控制、消费电子等多个领域有广泛的应用。这份datasheet是开发者理解和应用STM32F20x系列芯片的重要参考文档，能帮助他们充分利用芯片的各项功能，进行高效且可靠的系统设计。

Description STM32F205xx, STM32F207xx

16/163 Doc ID 15818 Rev 7

2.2.1 ARM

Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded

systems. It was developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced response to interrupts.

The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering

the high-performance expected from an ARM core in the memory size usually associated

with 8- and 16-bit devices.

With its embedded ARM core, the STM32F205xx and STM32F207xx family is compatible

with all ARM tools and software.

Figure 1 shows the general block diagram of the STM32F20x family.

2.2.2 Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data

protection. The MPU can manage up to 8 protection areas that can all be further divided up

into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes

of addressable memory.

The memory protection unit is especially helpful for applications where some critical or

certified code has to be protected against the misbehavior of other tasks. It is usually

managed by an RTOS (real-time operating system). If a program accesses a memory

location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS

environment, the kernel can dynamically update the MPU area setting, based on the

process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

2.2.3 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM

Cortex™-M3 processors. It balances the inherent performance advantage

of the ARM Cortex-M3 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher operating frequencies.

To release the processor full 150 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache which increases program

execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 120 MHz.

2.2.4 Embedded Flash memory

The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes,

512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data.

The devices also feature 512 bytes of OTP memory that can be used to store critical user

data such as Ethernet MAC addresses or cryptographic keys.

Description STM32F205xx, STM32F207xx

18/163 Doc ID 15818 Rev 7

2.2.9 DMA

The flexible 16-stream general-purpose DMAs (8 streams for DMA1 and 8 streams for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support

burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB)

and performance.

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals:

● SPI and I

● I

● USART and UART

● General-purpose, basic and advanced-control timers TIMx

● DAC

● SDIO

● Camera interface (DCMI)

● ADC.

2.2.10 FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F205xx and STM32F207xx family. It has four Chip

Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM,

NOR Flash and NAND Flash.

Functionality overview:

● Write FIFO

● Code execution from external memory except for NAND Flash and PC Card

● The targeted frequency, f

CLK

, is equal to HCLK/2, so external access is at 60 MHz

when HCLK is at 120 MHz and external access is at 30 MHz when HCLK is at 60 MHz

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

STM32F205xx, STM32F207xx Description

Doc ID 15818 Rev 7 19/163

2.2.11 Nested vectored interrupt controller (NVIC)

The STM32F205xx and STM32F207xx embed a nested vectored interrupt controller able to

handle up to 87 maskable interrupt channels (not including the 16 interrupt lines of the

Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low-latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving, higher-priority interrupts

● Support tail chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

2.2.12 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected

to the 16 external interrupt lines.

2.2.13 Clocks and startup

System clock selection is performed on startup, however, the 16 MHz internal RC oscillator

is selected as the default CPU clock on reset. An external 4-26 MHz clock can be selected,

in which case it is monitored for failure. If failure is detected, the system automatically

switches back to the internal RC oscillator. A software interrupt is generated if enabled.

Similarly, full interrupt management of the PLL clock entry is available when necessary (for

example if an indirectly used external oscillator fails).

The advanced clock controller clocks the core and all peripherals using a single crystal or

oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the

system clock.

Several prescalers and PLLs allow the configuration of the two AHB buses, the high-speed

APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two

AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is

60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz.

In order to achieve audio class performance, a specific crystal can be used. In this case, the

S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

Description STM32F205xx, STM32F207xx

20/163 Doc ID 15818 Rev 7

2.2.14 Boot modes

At startup, boot pins are used to select one out of three boot options:

● Boot from user Flash

● Boot from system memory

● Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB

OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

2.2.15 Power supply schemes

● V

= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through V

pins. On WLCSP package, V

ranges from

1.65 to 3.6 V.

● V

SSA

, V

DDA

= 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

RCs and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

● V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

Refer to Figure 17: Power supply scheme for more details.

Note: V

DDA

minimum value of 1.65 V is obtained when the device operates in a reduced

temperature range.

2.2.16 Power supply supervisor

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and

ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the

option byte loading process starts, either to confirm or modify default thresholds, or to

disable BOR permanently. Three BOR thresholds are available through option bytes.

The device remains in reset mode when V

is below a specified threshold, V

POR/PDR

BOR

, without the need for an external reset circuit. On devices in WLCSP package, BOR

can be inactivated by setting IRROFF to V

(see Section 2.2.17: Voltage regulator).

The device also features an embedded programmable voltage detector (PVD) that monitors

the V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

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