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首页CC3200单片无线MCU开发指南:全面解析与架构
CC3200单片无线MCU开发指南:全面解析与架构
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更新于2024-07-21
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CC3200是一款专为物联网(IoT)和Wi-Fi应用设计的单芯片无线微控制器,它集成了强大的处理器和多种功能模块,旨在简化开发过程。该datasheet主要涵盖了CC3200的技术参考手册,重点介绍其架构、核心组件和特性。
1. **架构概述**:文档首先介绍了CC3200的整体架构,包括处理器、内存、接口等关键部分。其中,处理器采用Cortex-M4,这是一种高性能的32位RISC架构,支持嵌入式系统所需的高效处理能力。内存部分包括闪存和RAM,以满足程序存储和实时数据处理的需求。
- **微控制器组件**:
- **处理器核心**:Cortex-M4负责执行指令,提供高级处理能力和低功耗模式。
- **内存**:包括闪存用于存储程序代码,RAM用于运行时数据操作。
- **uDMA控制器**:协助CPU进行快速的数据传输,提高外设间的通信效率。
- **通用定时器(GPT)**:用于精确的时间管理,支持多个独立计时器。
- **看门狗定时器(WDT)**:防止系统死锁,通过定期中断确保系统的稳定性。
- **音频串行端口(McASP)**:支持多通道音频输入输出,适合音频应用。
- **SPI、I2C、UART**:标准串行通信接口,便于与外部设备通信。
- **GPIO**:通用输入输出,实现各种功能如开关控制、信号指示等。
- **ADC**:模拟到数字转换器,用于信号采集和测量。
- **SD卡接口**:方便扩展存储容量或与外部SD卡交互。
- **相机接口**:支持并行接口,可以连接相机传感器。
- **调试接口**:用于硬件调试和故障排查。
- **硬件加密加速器**:增强安全性能,支持数据加密和解密。
- **电源管理**:集成的时钟、复位和电源管理模块,优化功耗。
2. **Cortex-M4处理器**:这部分深入阐述了处理器的核心结构,包括其内部组件和工作原理,以及与外围设备的交互方式。
- **系统级别集成**:CC3200的Cortex-M4处理器与其他模块紧密协作,确保系统功能的高效协同。
通过学习这份datasheet,开发人员能够了解如何充分利用CC3200的特性来构建物联网和Wi-Fi解决方案,从硬件配置到软件开发都能找到所需的信息。这对于理解和使用这款单片机在实际项目中的应用至关重要。
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7-22. I2CSMIS Register Field Descriptions .................................................................................. 207
7-23. I2CSICR Register Field Descriptions .................................................................................. 209
7-24. I2CSOAR2 Register Field Descriptions................................................................................ 211
7-25. I2CSACKCTL Register Field Descriptions ............................................................................ 212
7-26. I2CFIFODATA Register Field Descriptions............................................................................ 213
7-27. I2CFIFOCTL Register Field Descriptions.............................................................................. 214
7-28. I2CFIFOSTATUS Register Field Descriptions ........................................................................ 216
7-29. I2CPP Register Field Descriptions ..................................................................................... 217
7-30. I2CPC Register Field Descriptions ..................................................................................... 218
8-1. SPI Interface .............................................................................................................. 221
8-2. Phase and Polarity Combinations ...................................................................................... 223
8-3. Clock Ratio Granularity .................................................................................................. 228
8-4. Granularity Examples .................................................................................................... 228
8-5. SPI Word Length WL..................................................................................................... 228
8-6. SPI Registers.............................................................................................................. 245
8-7. SPI_SYSCONFIG Register Field Descriptions ....................................................................... 246
8-8. SPI_SYSSTATUS Register Field Descriptions ....................................................................... 247
8-9. SPI_IRQSTATUS Register Field Descriptions........................................................................ 248
8-10. SPI_IRQENABLE Register Field Descriptions........................................................................ 250
8-11. SPI_MODULCTRL Register Field Descriptions ...................................................................... 251
8-12. SPI_CHCONF Register Field Descriptions............................................................................ 252
8-13. SPI_CHSTAT Register Field Descriptions ............................................................................ 255
8-14. SPI_CHCTRL Register Field Descriptions ............................................................................ 256
8-15. SPI_TX Register Field Descriptions.................................................................................... 257
8-16. SPI_RX Register Field Descriptions.................................................................................... 258
8-17. SPI_XFERLEVEL Register Field Descriptions........................................................................ 259
9-1. Available CCP Pins and PWM Outputs/Signals Pins ................................................................ 262
9-2. General-Purpose Timer Capabilities ................................................................................... 263
9-3. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .................................... 264
9-4. 16-Bit Timer With Prescaler Configurations........................................................................... 265
9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode.......................................... 265
9-6. Counter Values When the Timer is Enabled in Input Event-Count Mode ......................................... 267
9-7. Counter Values When the Timer is Enabled in PWM Mode ........................................................ 268
9-8. TIMER Registers.......................................................................................................... 273
9-9. GPTMCFG Register Field Descriptions................................................................................ 274
9-10. GPTMTAMR Register Field Descriptions.............................................................................. 275
9-11. GPTMTBMR Register Field Descriptions.............................................................................. 277
9-12. GPTMCTL Register Field Descriptions ................................................................................ 279
9-13. GPTMIMR Register Field Descriptions ................................................................................ 281
9-14. GPTMRIS Register Field Descriptions................................................................................. 283
9-15. GPTMMIS Register Field Descriptions................................................................................. 285
9-16. GPTMICR Register Field Descriptions................................................................................. 287
9-17. GPTMTAILR Register Field Descriptions.............................................................................. 289
9-18. GPTMTBILR Register Field Descriptions.............................................................................. 290
9-19. GPTMTAMATCHR Register Field Descriptions ...................................................................... 291
9-20. GPTMTBMATCHR Register Field Descriptions ...................................................................... 292
9-21. GPTMTAPR Register Field Descriptions .............................................................................. 293
9-22. GPTMTBPR Register Field Descriptions .............................................................................. 294
9-23. GPTMTAPMR Register Field Descriptions............................................................................ 295
16
List of Tables SWRU367B–June 2014–Revised October 2014
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Copyright © 2014, Texas Instruments Incorporated
www.ti.com
9-24. GPTMTBPMR Register Field Descriptions............................................................................ 296
9-25. GPTMTAR Register Field Descriptions................................................................................ 297
9-26. GPTMTBR Register Field Descriptions................................................................................ 298
9-27. GPTMTAV Register Field Descriptions ................................................................................ 299
9-28. GPTMTBV Register Field Descriptions ................................................................................ 300
9-29. GPTMDMAEV Register Field Descriptions............................................................................ 301
10-1. Watchdog Timers Register Map ........................................................................................ 306
10-2. WATCHDOG Registers .................................................................................................. 307
10-3. WDTLOAD Register Field Descriptions................................................................................ 308
10-4. WDTVALUE Register Field Descriptions .............................................................................. 309
10-5. WDTCTL Register Field Descriptions.................................................................................. 310
10-6. WDTICR Register Field Descriptions .................................................................................. 311
10-7. WDTRIS Register Field Descriptions .................................................................................. 312
10-8. WDTTEST Register Field Descriptions ................................................................................ 313
10-9. WDTLOCK Register Field Descriptions................................................................................ 314
11-1. Card Types ................................................................................................................ 325
11-2. Throughput Data .......................................................................................................... 325
12-1. ulIntFlags Parameter ..................................................................................................... 342
12-2. ulStatFlags Parameter ................................................................................................... 342
13-1. ADC Registers ............................................................................................................ 348
13-2. ADC_MODULE Registers ............................................................................................... 349
13-3. ADC_CTRL Register Field Descriptions............................................................................... 350
13-4. ADC_CH0_IRQ_EN Register Field Descriptions ..................................................................... 351
13-5. ADC_CH2_IRQ_EN Register Field Descriptions ..................................................................... 352
13-6. ADC_CH4_IRQ_EN Register Field Descriptions ..................................................................... 353
13-7. ADC_CH6_IRQ_EN Register Field Descriptions ..................................................................... 354
13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions .............................................................. 355
13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions .............................................................. 356
13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions .............................................................. 357
13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions .............................................................. 358
13-12. ADC_DMA_MODE_EN Register Field Descriptions ................................................................. 359
13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions ..................................................... 360
13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.................................................... 361
13-15. CHANNEL0FIFODATA Register Field Descriptions ................................................................. 362
13-16. CHANNEL2FIFODATA Register Field Descriptions ................................................................. 363
13-17. CHANNEL4FIFODATA Register Field Descriptions ................................................................. 364
13-18. CHANNEL6FIFODATA Register Field Descriptions ................................................................. 365
13-19. ADC_CH0_FIFO_LVL Register Field Descriptions................................................................... 366
13-20. ADC_CH2_FIFO_LVL Register Field Descriptions................................................................... 367
13-21. ADC_CH4_FIFO_LVL Register Field Descriptions................................................................... 368
13-22. ADC_CH6_FIFO_LVL Register Field Descriptions................................................................... 369
13-23. ADC_CH_ENABLE Register Field Descriptions...................................................................... 370
13-24. ulChannel Tags ........................................................................................................... 371
13-25. ulIntFlags Tags............................................................................................................ 371
14-1. Image sensor interface signals.......................................................................................... 379
14-2. Ratio of the XCLK Frequency Generator .............................................................................. 383
14-3. CAMERA REGISTERS .................................................................................................. 386
14-4. CC_SYSCONFIG Register Field Descriptions........................................................................ 387
14-5. CC_SYSSTATUS Register Field Descriptions........................................................................ 388
17
SWRU367B–June 2014–Revised October 2014 List of Tables
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Copyright © 2014, Texas Instruments Incorporated
www.ti.com
14-6. CC_IRQSTATUS Register Field Descriptions ........................................................................ 389
14-7. CC_IRQENABLE Register Field Descriptions ........................................................................ 391
14-8. CC_CTRL Register Field Descriptions................................................................................. 393
14-9. CC_CTRL_DMA Register Field Descriptions ......................................................................... 395
14-10. CC_CTRL_XCLK Register Field Descriptions ........................................................................ 396
14-11. CC_FIFODATA Register Field Descriptions .......................................................................... 397
15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN) ........ 410
15-2. Peripheral Macro Table .................................................................................................. 419
15-3. PRCM Registers .......................................................................................................... 420
15-4. CAMCLKCFG Register Field Descriptions ............................................................................ 422
15-5. CAMCLKEN Register Field Descriptions .............................................................................. 423
15-6. CAMSWRST Register Field Descriptions ............................................................................. 424
15-7. MCASPCLKEN Register Field Descriptions........................................................................... 425
15-8. MCASPSWRST Register Field Descriptions.......................................................................... 426
15-9. SDIOMCLKCFG Register Field Descriptions ......................................................................... 427
15-10. SDIOMCLKEN Register Field Descriptions ........................................................................... 428
15-11. SDIOMSWRST Register Field Descriptions........................................................................... 429
15-12. APSPICLKCFG Register Field Descriptions .......................................................................... 430
15-13. APSPICLKEN Register Field Descriptions ............................................................................ 431
15-14. APSPISWRST Register Field Descriptions ........................................................................... 432
15-15. DMACLKEN Register Field Descriptions .............................................................................. 433
15-16. DMASWRST Register Field Descriptions ............................................................................. 434
15-17. GPIO0CLKEN Register Field Descriptions............................................................................ 435
15-18. GPIO0SWRST Register Field Descriptions ........................................................................... 436
15-19. GPIO1CLKEN Register Field Descriptions............................................................................ 437
15-20. GPIO1SWRST Register Field Descriptions ........................................................................... 438
15-21. GPIO2CLKEN Register Field Descriptions............................................................................ 439
15-22. GPIO2SWRST Register Field Descriptions ........................................................................... 440
15-23. GPIO3CLKEN Register Field Descriptions............................................................................ 441
15-24. GPIO3SWRST Register Field Descriptions ........................................................................... 442
15-25. GPIO4CLKEN Register Field Descriptions............................................................................ 443
15-26. GPIO4SWRST Register Field Descriptions ........................................................................... 444
15-27. WDTCLKEN Register Field Descriptions .............................................................................. 445
15-28. WDTSWRST Register Field Descriptions ............................................................................. 446
15-29. UART0CLKEN Register Field Descriptions ........................................................................... 447
15-30. UART0SWRST Register Field Descriptions........................................................................... 448
15-31. UART1CLKEN Register Field Descriptions ........................................................................... 449
15-32. UART1SWRST Register Field Descriptions........................................................................... 450
15-33. GPT0CLKCFG Register Field Descriptions ........................................................................... 451
15-34. GPT0SWRST Register Field Descriptions ............................................................................ 452
15-35. GPT1CLKEN Register Field Descriptions ............................................................................. 453
15-36. GPT1SWRST Register Field Descriptions ............................................................................ 454
15-37. GPT2CLKEN Register Field Descriptions ............................................................................. 455
15-38. GPT2SWRST Register Field Descriptions ............................................................................ 456
15-39. GPT3CLKEN Register Field Descriptions ............................................................................. 457
15-40. GPT3SWRST Register Field Descriptions ............................................................................ 458
15-41. MCASPCLKCFG0 Register Field Descriptions ....................................................................... 459
15-42. MCASPCLKCFG1 Register Field Descriptions ....................................................................... 460
15-43. I2CLCKEN Register Field Descriptions................................................................................ 461
18
List of Tables SWRU367B–June 2014–Revised October 2014
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Copyright © 2014, Texas Instruments Incorporated
www.ti.com
15-44. I2CSWRST Register Field Descriptions ............................................................................... 462
15-45. LPDSREQ Register Field Descriptions ................................................................................ 463
15-46. TURBOREQ Register Field Descriptions.............................................................................. 464
15-47. DSLPWAKECFG Register Field Descriptions ........................................................................ 465
15-48. DSLPTIMRCFG Register Field Descriptions.......................................................................... 466
15-49. SLPWAKEEN Register Field Descriptions ............................................................................ 467
15-50. SLPTMRCFG Register Field Descriptions ............................................................................ 468
15-51. WAKENWP Register Field Descriptions............................................................................... 469
15-52. RCM_IS Register Field Descriptions................................................................................... 470
15-53. RCM_IEN Register Field Descriptions ................................................................................. 471
16-1. GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) ................................... 473
16-2. GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53....................................... 474
16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25 C).................................................. 475
16-4. Analog Mux Control Registers and Bits................................................................................ 478
16-5. Board Level Behavior .................................................................................................... 479
16-6. GPIO/Pins Available for Application.................................................................................... 480
16-7. Pin Multiplexing ........................................................................................................... 483
16-8. Pin Groups for I2S........................................................................................................ 497
16-9. Pin Groups for SPI........................................................................................................ 497
16-10. Pin Groups for SD-Card I/F ............................................................................................. 497
16-11. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description ...................................... 498
16-12. Recommended Pin Multiplexing Configurations ...................................................................... 500
16-13. Sense on Power Configurations ........................................................................................ 504
A-1. Peripheral Samples....................................................................................................... 505
B-1. Miscellaneous Register Summary ...................................................................................... 506
B-2. DMA_IMR Register Field Descriptions................................................................................. 507
B-3. DMA_IMS Register Field Descriptions................................................................................. 509
B-4. DMA_IMC Register Field Descriptions................................................................................. 511
B-5. DMA_ICR Register Field Descriptions ................................................................................. 513
B-6. DMA_MIS Register Field Descriptions................................................................................. 515
B-7. DMA_RIS Register Field Descriptions ................................................................................. 517
B-8. GPTTRIGSEL Register Field Descriptions ............................................................................ 519
19
SWRU367B–June 2014–Revised October 2014 List of Tables
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Copyright © 2014, Texas Instruments Incorporated
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