Technical Article
.
Understanding Spurious-Free
Dynamic Range in Wideband
GSPS ADCs
by Ian Beavers, contributing technical expert,
Analog Devices, Inc.
Many analog input specifications should be considered when
selecting a wideband analog-to-digital converter (ADC) for
a high performance system, such as ADC resolution,
sample rate, signal-to-noise ratio (SNR), effective number of
bits (ENOB), input bandwidth, spurious free dynamic range
(SFDR), and differential or integral nonlinearity.
For gigasample per second (GSPS) ADCs, perhaps one of the
most important ac performance specifications is SFDR. It
defines the capability of the ADC and the system to decipher
a carrier signal from other noise or any other spurious
frequency.
To achieve the conversion speed used in GSPS ADCs,
several architectures that capture signals at a high sample
rate of interest can be employed. However, some of these
architectures are used at the expense of full bandwidth SFDR
performance.
To understand the impact of the converter SFDR on the
system, we answered some common questions from design
engineers about the details of the SFDR specification, how it
is described in converter datasheets, the architectures that
limit or maximize the ADC performance, and system design
aspects that limit SFDR performance.
I have seen SFDR stated in data sheets with and without
caveats. What exactly is SFDR?
Being able to discern a signal from the noise is a key aspect
of many signal acquisition systems. Whether it is a defined
telecommunications protocol, a radar sweep, or
measurement instrumentation, acquiring and deciphering
weak signals is at the heart of any differentiating system
performance.
SFDR represents the smallest power signal that can be
distinguished from a large interfering signal. It defines the
dynamic ratio between the root mean square (rms) value of
the power of a carrier and the rms value of the next most
significant spurious signal seen in the frequency domain,
such as in a fast Fourier transform (FFT). Hence, by
definition, this dynamic range must be free of other spurious
frequencies, or spurs.
SFDR is often quantified as the range, in units of power
(dBc), relative from the carrier of interest to the power of the
next most significant frequency. However, it also could be
referenced to a full-scale signal in units of power (dBFS).
This is an important distinction since the carrier of interest
may be a relatively lower power signal that is well below the
full-scale input to the ADC. When this is the case, the SFDR
becomes paramount in distinguishing the signal from other
noise and spurious frequencies.
What limits the SFDR of an ADC?
A harmonic frequency is an integer multiple of the
fundamental frequency. For a well designed monolithic
ADC core, the SFDR typically will be dominated by the
dynamic range between a carrier frequency and the second
or third harmonic of the fundamental frequency of interest.
Some narrow-band ADC data sheets will define the SFDR
only in the narrow band of operation, typically when the
second and third harmonics fall out of band. Other data
sheets may describe SFDR over a wide bandwidth with
caveats as to what conditions need to exist for this
performance.
Although the second or third harmonic may typically be the
dominant spurious frequency, there are spurs that could also
limit the SFDR performance of a GSPS ADC due to other
system reasons. For example, multiple interleaved ADC
cores can create spurious frequencies by the introduction of
interleaving artifacts into the frequency domain. These can
have the potential to be larger in magnitude than the second
or third harmonic of the fundamental frequency. Therefore,
they would be the dominant limiting factor for SFDR.
Although it may seem counterintuitive, SFDR could also be
specified in an interleaved ADC data sheet with the
admonition that interleaving spurs are excluded from the
calculation (Figure 1).
www.analog.com
Page 1 of 4 ©2014 Analog Devices, Inc. All rights reserved.