GSPS ADCs：理解宽频带器件的无杂散动态范围关键

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在高速模拟到数字转换器（GSPS ADCs）的选择过程中，理解无杂散动态范围（Spurious-Free Dynamic Range, SFDR）的重要性至关重要。作为一项关键性能指标，SFDR衡量了ADC和系统在解析信号时消除噪声和其他额外频率成分的能力，特别是在宽频带应用中。它直接影响系统的整体性能和信号质量。对于每秒10亿次采样（Gigasample per second, GSPS）的ADC，高SFDR是确保信号完整性、防止潜在干扰和保持信号精确度的关键因素。由于GSPS ADCs通常采用高速采样技术，如并行或流水线架构，这些架构可以实现极高的转换速度，但同时也可能牺牲部分SFDR特性，特别是在处理全带宽信号时。为了全面评估SFDR对系统设计的影响，我们深入了解了这个指标的细节，并回答了一些来自设计工程师的常见问题，包括： 1. 定义与测量方法：SFDR通常定义为ADC能够抑制高于有用信号的最远非本振频率分量的信号强度与有用信号的比值，通常以dBc（对数分贝，差分信噪比）表示。 2. 架构影响：不同的GSPS ADC架构，如逐次比较型ADC、折叠ADC或者交错ADC，其内部噪声源、量化噪声以及混频效应会影响SFDR。例如，折叠ADC虽然能提高速度，但可能会引入额外的频率混叠，降低SFDR。 3. 线性度与非线性失真：集成的线性和非线性特性也会影响SFDR。理想的ADC应具有低的失调和优良的线性特性，以减小失真并提升SFDR。 4. 系统级考虑：除了ADC本身的SFDR外，系统级设计，如滤波器、放大器和解调电路，都会共同决定最终的可用性能。优化这些组件可以补偿ADC的SFDR限制。 5. 功耗与成本：追求高SFDR有时会增加系统成本和功耗，因此，在实际应用中需要权衡性能与经济性。设计师在选择GSPS ADC时，必须仔细权衡各种规格，包括SFDR，以确保系统能够满足高性能需求，同时保持信号质量和抗干扰能力。通过深入理解SFDR的含义、影响因素以及如何优化设计，工程师能够更好地应对挑战，实现高效、可靠的宽带信号处理。

Technical Article

MS-2660

Understanding Spurious-Free

Dynamic Range in Wideband

GSPS ADCs

by Ian Beavers, contributing technical expert,

Analog Devices, Inc.

Many analog input specifications should be considered when

selecting a wideband analog-to-digital converter (ADC) for

a high performance system, such as ADC resolution,

sample rate, signal-to-noise ratio (SNR), effective number of

bits (ENOB), input bandwidth, spurious free dynamic range

(SFDR), and differential or integral nonlinearity.

For gigasample per second (GSPS) ADCs, perhaps one of the

most important ac performance specifications is SFDR. It

defines the capability of the ADC and the system to decipher

a carrier signal from other noise or any other spurious

frequency.

To achieve the conversion speed used in GSPS ADCs,

several architectures that capture signals at a high sample

rate of interest can be employed. However, some of these

architectures are used at the expense of full bandwidth SFDR

performance.

To understand the impact of the converter SFDR on the

system, we answered some common questions from design

engineers about the details of the SFDR specification, how it

is described in converter datasheets, the architectures that

limit or maximize the ADC performance, and system design

aspects that limit SFDR performance.

I have seen SFDR stated in data sheets with and without

caveats. What exactly is SFDR?

Being able to discern a signal from the noise is a key aspect

of many signal acquisition systems. Whether it is a defined

telecommunications protocol, a radar sweep, or

measurement instrumentation, acquiring and deciphering

weak signals is at the heart of any differentiating system

performance.

SFDR represents the smallest power signal that can be

distinguished from a large interfering signal. It defines the

dynamic ratio between the root mean square (rms) value of

the power of a carrier and the rms value of the next most

significant spurious signal seen in the frequency domain,

such as in a fast Fourier transform (FFT). Hence, by

definition, this dynamic range must be free of other spurious

frequencies, or spurs.

SFDR is often quantified as the range, in units of power

(dBc), relative from the carrier of interest to the power of the

next most significant frequency. However, it also could be

referenced to a full-scale signal in units of power (dBFS).

This is an important distinction since the carrier of interest

may be a relatively lower power signal that is well below the

full-scale input to the ADC. When this is the case, the SFDR

becomes paramount in distinguishing the signal from other

noise and spurious frequencies.

What limits the SFDR of an ADC?

A harmonic frequency is an integer multiple of the

fundamental frequency. For a well designed monolithic

ADC core, the SFDR typically will be dominated by the

dynamic range between a carrier frequency and the second

or third harmonic of the fundamental frequency of interest.

Some narrow-band ADC data sheets will define the SFDR

only in the narrow band of operation, typically when the

second and third harmonics fall out of band. Other data

sheets may describe SFDR over a wide bandwidth with

caveats as to what conditions need to exist for this

performance.

Although the second or third harmonic may typically be the

dominant spurious frequency, there are spurs that could also

limit the SFDR performance of a GSPS ADC due to other

system reasons. For example, multiple interleaved ADC

cores can create spurious frequencies by the introduction of

interleaving artifacts into the frequency domain. These can

have the potential to be larger in magnitude than the second

or third harmonic of the fundamental frequency. Therefore,

they would be the dominant limiting factor for SFDR.

Although it may seem counterintuitive, SFDR could also be

specified in an interleaved ADC data sheet with the

admonition that interleaving spurs are excluded from the

calculation (Figure 1).

www.analog.com

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