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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, VOL. XX, NO. X, XX. 2015 3
commercial methods are limited to the protection of single
large FPGA configurations; 2)they cannot support the pay-
per-device licensing; 3) the previous encryption-based HWIP
protection methods require permanent key storage and on-chip
cryptographic decryption modules to decrypt the bitstream,
which introduces some security vulnerabilities and high over-
head. Our approach overcomes these limitations.
B. Metering ASIC Intellectual Properties
A number of watermarking methods for ASIC/FPGA in-
tellectual property protection have been proposed [32]-[35].
However, watermarking techniques are passive and only used
to identify the intellectual property. In 2001, Koushanfar and
Qu [38] proposed the first hardware metering method that can
enable the design house to gain the post-fabrication control by
passive or active control of the number of produced ICs. Yous-
ra et al. [24] proposed an anti-overbuilding mechanism which
exploits the functional description of the design and the unique
and unclonable IC identifiers. The locks can be embedded
via modifying the hardware computational model such as an
FSM. They also presented another FSM manipulation method
[25] which introduces only a few new states. These solutions
are only suitable for protecting single ASIC chips. Later on,
they further extended their scheme to actively control multiple
IP cores [26] for ASIC chips. Recently, Koushanfar [27]
improved again the locking structure in [24] by a multi-point
function. Meanwhile, Roy et al. [20] presented another kind of
cryptography-based metering methods, but their solution has a
very high overhead. These metering mechanisms are designed
for anti-overbuilding ASIC devices, they are not appropriate
for pay-per-device licensing of FPGA designs.
In this paper, our proposed FPGA HWIP binding technique
not only addresses the main drawbacks of the traditional FPGA
HWIP protection methods, it can also support a pay-per-
device licensing scheme. This provides technical support for
the product developers (system developers) to pay IP licensing
fees only for the FPGA devices they are using. It also enables
the IP vendors to freely distribute their IPs because they can
ensure that the distributed IPs run only on specific FPGAs
rather than all the FPGAs. This binding scheme brings a
remarkable advantage for the IP-based business model: the
IP owners can take the full control over the use of their
IP cores and protect them from unlicensed use; the FPGA-
based product developers who could not afford the expensive
unlimited IP license are now also able to obtain a number of
single instances of the required IP cores at a much lower cost.
III. PRELIMINARIES
In this section, we will introduce the general terms and
concepts used throughout the paper. More specific definitions
would be described as necessary.
A. Physical Unclonable Function (PUF)
PUF provides a unique chip-dependent mapping from a set
of digital inputs (challenges) to a set of digital outputs (re-
sponses) based on the unclonable properties of the underlying
physical device. Although it is difficult to come up with a
uniform definition for all types of PUFs, they should all satisfy
the following properties [39]:
• Persistent and unpredictable. The response (R
i
) to a
challenge (C
i
) is random and unpredictable, but should
remain the same for the same challenge over multiple
observations.
• Unclonable. It is impossible to obtain R
i
from C
i
with-
out the physical presence of the PUF. In other words,
given a PUF, it is infeasible for an adversary to build
another PUF that provides the same responses to every
possible challenge. This is assumed to be true due to the
uncontrollable technology variations.
• Tamper evident. Invasive attacks to PUFs will destroy the
PUFs and thus can be detected easily.
Because of those properties, PUF has become an efficient
mechanism to address security and trust problems in many
applications, such as binding software IPs to specific FPGAs
[11], hardware/software authentication [16], FPGA IP protec-
tion [18], [43], anti-overbuilding [24]-[27] and resisting FPGA
replay attacks [36].
B. Finite State Machine (FSM)
FSM is a popular model for sequential systems. In this
paper, we employ FSMs to bind HWIPs to the FPGAs with
PUFs to restrict the HWIP’s usage so that it can only work
on the enrolled FPGA devices. Similar to the FSM-based
works such as [15], [24]-[27], the method proposed in this
paper is not applicable to some high-speed designs that do
not have FSMs. These high-speed designs are normally small
dedicated modules such as digital filters, channel equalizers,
address decoders and arithmetic logic units. Fortunately, for
the HWIPs in industrial designs that we target to protect, the
sequential components or functions, and therefore FSMs, are
ubiquitous [15].
C. Parties Involved in HWIP Binding
In order to facilitate our study, we consider the following
parties involved in the binding mechanism and their respective
roles:
• FPGA vendor (FV): FV designs and manufactures un-
configured FPGA devices and can securely deploy PUF
in the fabric of these devices.
• System developer (SD): SD integrates the third-party IPs
along with their own designs to create a commercial prod-
uct on an FPGA chip. The product will be synthesized
into a configuration bitstream file for the FPGA chip to
download using the computer aided design (CAD) tools
provided by the FV.
• IP core vendor (CV): CV creates innovative logic circuits
(HWIP cores) and sells them to SDs for profits. CV needs
an effective technique to keep the full control over the use
of the HWIP cores.
• End user (EU): EU purchases the FPGA products de-
veloped by the SD. The SD expects that EUs cannot
‘clone’ the products by copying the FPGA configuration
bitstream file and run on unauthorized FPGA devices.