CLRC663：多协议NFC前端芯片， RFID开发全面指南

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CLRC663是一款高性能的多协议NFC前端芯片，专为RFID开发学习者设计，旨在提供全面的NFC功能支持。该芯片具备以下主要特性： 1. **多种操作模式**：CLRC663支持ISO/IEC 14443A标准（适用于MIFARE卡和读写器），包括读写模式，这使得它能够与常见的MIFARE Classic 1K、4K、Ultralight、Ultralight C、PLUS和DES Fire产品无缝协作。此外，它还兼容ISO/IEC 14443B协议，支持日本JIS X 6319-4标准（类似于Felica 1），并且在被动发起模式下遵循ISO/IEC 18092协议。 2. **高效通信**：内置的发射器使芯片能够在不额外增加主动电路的情况下驱动ISO/IEC 14443A标准的卡片和应答器进行通信。数字模块负责整个ISO/IEC 14443A帧结构的管理和错误检测功能，包括奇偶校验和循环冗余校验（CRC）。 3. **高速传输**：CLRC663支持MIFARE产品的高数据传输速度，最高可达双向848 kbit/s，这对于处理大量数据或实现快速交换极其重要。 4. **兼容其他标准**：除了MIFARE系列，它还支持ISO/IEC 15693和ICODE EPC UID/EPC OTP标准，以及ISO/IEC 18000-3模式3（EPC Class-1 HF），进一步扩大了其应用范围，适应不同类型的RFID标签和系统。 5. **层2和3支持**：CLRC663不仅提供了底层的数据传输功能，还支持ISO/IEC 18000-3等协议的高层功能，使得在构建复杂的应用时能够简化集成过程。 CLRC663作为一款多功能的NFC前端芯片，为开发者提供了强大的技术支持，无论是基础的MIFARE卡交互，还是对更高性能和多样标准的支持，都使得它成为RFID项目中的理想选择。通过理解和掌握这款芯片的工作原理和特性，开发者可以更有效地开发出兼容性良好、性能卓越的RFID解决方案。

Product data sheet

COMPANY PUBLIC

Rev. 4.4 — 2 May 2017

171144 16 of 159

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend

7.3.4 ISO/IEC15693 functionality

The physical parameters are described in Table 10.

[1] Fast inventory (page) read command only (ICODE proprietary command).

Table 10. Communication overview for ISO/IEC 15693 reader/writer reader to label

Communication

direction

Signal type Transfer speed

fc / 8192 kbit/s fc / 512 kbit/s

Reader to label (send

data from the

CLRC663 to a card)

reader side

modulation

10 % to 30 % ASK or

100 % ASK

10 % to 30 % ASK 90 %

to 100 % ASK

bit encoding 1/256 1/4

data rate 1.66 kbit/s 26.48 kbit/s

Table 11. Communication overview for ISO/IEC 15693 reader/writer label to reader

Communication

direction

Signal type Transfer speed

6.62 (6.67) kbit/s 13.24

kbit/s

[1]

26.48

(26.69) kbit/s

52.96 kbit/s

Label to reader

(CLRC663

receives data

from a card)

fc = 13.56 MHz

card side

modulation

not supported not supported single (dual)

subcarrier

load

modulation

ASK

single

subcarrier

load

modulation

ASK

bit length

(s)

- - 37.76 (37.46) 18.88

bit encoding - - Manchester

coding

Manchester

coding

subcarrier

frequency

[MHz]

--fc/32

(fc / 28)

fc / 32

Fig 10. Data coding according to ISO/IEC 15693. standard mode reader to label

001aam272

pulse

modulated

carrier

~9.44 μs

1 2 3 4

~18.88 μs

. 2 . . . ..... . . . . . . . . . 22..... 2 2

25555

~4,833 ms

3245

Product data sheet

COMPANY PUBLIC

Rev. 4.4 — 2 May 2017

171144 17 of 159

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend

7.3.5 EPC-UID/UID-OTP functionality

The physical parameters are described in Table 12.

Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientific

and medical) Band Class 1 Radio Frequency Identification Tag Interface Specification

(Candidate Recommendation, Version 1.0.0).

7.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF functionality

The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For a

detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1

HF standard.

7.3.6.1 Data encoding ICODE

The ICODE protocols have mainly three different methods of data encoding:

• “1” out of “4” coding scheme

• “1” out of “256” coding scheme

• “Return to Zero” (RZ) coding scheme

Data encoding for all three coding schemes is done by the ICODE generator.

The supported EPC Class-1 HF modes are:

• 2 pulse for 424 kbit subcarrier

• 4 pulse for 424 kbit subcarrier

• 2 pulse for 848 kbit subcarrier

• 4 pulse for 848 kbit subcarrier

7.3.7 ISO/IEC 18092 mode

The CLRC663 supports Passive Initiator Communication mode at the transfer speeds

106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.

• Passive communication mode means that the target answers to an initiator command

in a load modulation scheme. The initiator is active in terms of generating the RF field.

• Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092

communication.

Table 12. Communication overview for EPC/UID

Communication

direction

Signal type Transfer speed

26.48 kbit/s 52.96 kbit/s

Reader to card (send

data from the

CLRC663 to a card)

reader side modulation 10 % to 30 % ASK

bit encoding RTZ

bit length 37.76 s

Card to reader

(CLRC663 receives

data from a card)

card side modulation single subcarrier load

modulation

bit length 18.88 s

bit encoding Manchester coding

Product data sheet

COMPANY PUBLIC

Rev. 4.4 — 2 May 2017

171144 20 of 159

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend

The CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has to

be generated by the master. Data communication from the master to the slave uses the

Line MOSI. Line MISO is used to send data back from the CLRC663 to the master.

A serial peripheral interface (SPI compatible) is supported to enable high-speed

communication to a host. The implemented SPI compatible interface is according to a

standard SPI interface. The SPI compatible interface can handle data speed of up to 10

Mbit/s. In the communication with a host, CLRC663 acts as a slave receiving data from

the external host for register settings and to send and receive data relevant for the

communication on the RF interface.

NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,

the interface is disabled and reset. Between every SPI command, the NSS must go to

logical high to be able to start the next command read or write.

On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line

shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling

edge. The same is valid for the MISO line. Data is provided by the CLRC663 on the falling

edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.

7.4.2.2 Read data

To read out data from the CLRC663 by using the SPI compatible interface, the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Remark: The Most Significant Bit (MSB) has to be sent first.

7.4.2.3 Write data

To write data to the CLRC663 using the SPI interface, the following byte order has to be

used. It is possible to write more than one byte by sending a single address byte

(see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

Remark: The Most Significant Bit (MSB) has to be sent first.

7.4.2.4 Address byte

The address byte has to fulfill the following format:

The LSB bit of the first byte defines the used mode. To read data from the CLRC663, the

LSB bit is set to logic 1. To write data to the CLRC663, the LSB bit has to be cleared. The

bits 6 to 0 define the address byte.

Table 16. Byte Order for MOSI and MISO

byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1

MOSI address 0 address 1 address 2 …….. address n 00h

MISO X data 0 data 1 …….. data n  1 data n

Table 17. Byte Order for MOSI and MISO

byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1

MOSI address 0 data 0 data 1 …….. data n 1data n

MISO X X X …….. X X

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CLRC663：多协议NFC前端芯片， RFID开发全面指南

CLRC663设计参考原理图

CLRC663原理图+PCB

CLRC663中文技术手册

CLRC663-数据手册.pdf

CLRC663-Datasheet.pdf

CLRC663_CN.zip_CLRC663_CLRC663 中文_RFID 中文 CLRC663

CLRC663.pdf

CLRC663英文版3.4.pdf 网上目前找不到

CLRC663.pdf官方资料

AN11783 CLRC663 plus Low Power Card Detection.pdf

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