About This Book
MPC8548E Configurable Development System Reference Manual, Rev. 2
xvi Freescale Semiconductor
• Appendix F, “CDS Carrier Schematics, Rev. 1.3”
• Appendix G, “CDS CDC BOM”
• Appendix H, “CDS CPU Schematics (CDC)”
• Appendix I, “CDS I/O Board Schematics”
• Appendix J, “CDS Arcadia 3.0 BOM”
• Appendix K, “CDS Arcadia 3.0 Schematics”
• Appendix L, “CDS Arcadia 3.1 BOM”
• Appendix M, “CDS Arcadia 3.1 Schematics”
• Appendix N, “Installation Guide for the 12-V DC Power Supply Extension Cable”
• This reference manual also includes a glossary.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation provides useful information about the CDS architecture:
• The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html.
• Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and
David A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, by
David A. Patterson and John L. Hennessy.
Signal Conventions
OVERBAR An overbar indicates that a signal is active-low.
lowercase_italics Lowercase italics is used to indicate internal signals.
lowercase_plaintext Lowercase plain text is used to indicate signals that are used for configuration.
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term Description
ATM Asynchronous transfer mode
Carrier HIP-compliant HIPcard such as CDS, Elysium, etc.
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