RTD2120L：8051嵌入式微控制器详解与PDF技术资料

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RTD2120L是一款由Realtek公司设计的嵌入式微控制器，专为显示器市场开发，其技术规格和文档详细描述了这款产品的特性及功能。该芯片的核心基于Synopsys的DW8051设计，兼容8051系列工业标准，确保了与市场上其他8051产品良好的兼容性。它采用TSMC的0.18微米工艺，内置96K字节的Flash存储器，分为64KB程序空间和32KB参数保存区域，以满足不同应用的需求。 RTD2120L的主要特点包括： 1. 电压范围：工作电压范围宽广，支持3.0V至3.6V，适应不同的电源环境。 2. 高性能CPU：搭载8051核心，最高运行频率可达50MHz，具有4个时钟周期完成一个机器周期，展现出高效的计算性能。 3. 内存容量：内置256字节的内部RAM，外置512字节数据RAM，其中包含256字节的专用显示控制RAM（DDCRAM）和256字节的一般用途RAM，为系统提供了足够的存储空间。 4. 闪存存储：拥有96K字节的闪存，分为程序存储区和参数存储区，有利于程序加载和配置设置。 5. 接口支持：具备两个符合VESADDC1/2B/2Bi/CI标准的数字显示控制器接口，便于与显示器或其他外部设备通信。 6. 音频处理能力：芯片内建有三个可编程频率的PWM DAC通道，范围从100kHz到1MHz，适用于驱动高质量音频输出或音频信号处理。此外，RTD2120L提供了两种封装选择，即PLCC44或LQFP48，用户可以根据项目需求选择单独的微控制器模块或者集成到显示器控制板中，以节省包装成本和印刷电路板材料。总体来说，RTD2120L作为一款高度集成的微控制器，适合在显示器控制领域中提供高效、稳定且成本效益高的解决方案。对于开发者而言，理解并掌握这款芯片的特性和接口规范是设计相关应用系统的关键。若需获取更多详细信息，可通过访问Realtek官方网页www.oootec.cn获取最新版本的资料更新。

Realtek RTD2120

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DW8051 micro-processor

The DW8051 contained in RTD2120 is compatible with industry standard 803x/805x and

provides the following design features and enhancements to the standard 8051 microcontroller:

1. High speed architecture

Compared to standard 8051, the DW8051 processor core provides increased performance by

executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard

8051. The shortened bus timing improves the instruction execution rate for most instructions by a

factor of three over the standard 8051 architectures. The average speed improvement for the entire

instruction set is approximately 2.5X.

2. Stretch Memory Cycles

The stretch memory cycle feature enables application software to adjust the speed of data

memory access. The DW8051 can execute the MOVX instruction in as little as 2 instruction cycles.

However, it is sometimes desirable to stretch this value; for example, to access slow memory or slow

memory-mapped peripherals such as UARTs or LCDs.

The three LSBs of the Clock Control Register (at SFR location 8Eh) control the stretch value.

You can use stretch values between zero and seven. A stretch value of zero adds zero instruction

cycles, resulting in MOVX instructions executing in two instruction cycles. A stretch value of seven

adds seven instruction cycles, resulting in MOVX instructions executing in nine instruction cycles.

The stretch value can be changed dynamically under program control.

By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory

access, the software must set the stretch value to zero. The stretch value affects only data memory

access. The only way to reduce the speed of program memory (ROM) access is to use a slower clock.

3. Dual Data Pointers

The DW8051 employs dual data pointers to accelerate data memory block moves. The standard

8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The

DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h. It is not

necessary to modify code to use DPTR0.

The DW8051 adds a second data pointer (DPTR1) at SFR locations 84h and 85h. The SEL bit in

the DPTR Select register, DPS (SFR 86h), selects the active pointer. When SEL = 0, instructions that

use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use

DPL1 and DPH1. SEL is the bit 0 of SFR location 86h. No other bits of SFR location 86h are used.

All DPTR-related instructions use the currently selected data pointer. To switch the active

pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).

This requires only one instruction to switch from a source address to a destination address, saving

application code from having to save source and destination addresses when doing a block move.

Using dual data pointers provides significantly increased efficiency when moving large blocks of

data.

4. Timer Rate Control

One important difference exists between the RTD2120 and 80C32 regarding timers. The original

80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud

rates(depending on the mode). The RTD2120 architecture normally runs using 4 clocks per cycle.

However, in the area of timers, it will default to a 12 clock per cycle scheme on a reset. This allows

existing code with real–time dependencies such as baud rates to operate properly. If an application

needs higher speed timers or serial baud rates, the timers can be set to run at the 4 clock rate.

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