W25X系列串行Flash存储器产品介绍

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华邦 W25x Serial Flash 存储解决方案华邦 W25x Serial Flash 存储器是一种存储解决方案，适用于空间有限、引脚少、功耗低的系统。该系列产品提供了灵活性和性能，远超普通的 Serial Flash 设备。它们非常适合代码下载应用程序，以及存储语音、文本和数据。 **特点** * 提供 1M-bit、2M-bit、4M-bit 和 8M-bit 的存储容量选择 * 单 2.7V 到 3.6V 电源供应，低至 5mA 的活动电流和 1µA 的待机电流 * 小巧的封装设计，适合空间有限的应用场景 * 双输出 SPI 界面，提供高速数据传输 * 支持 HOLD 功能，能够暂停数据传输 **引脚配置** 华邦 W25x Serial Flash 存储器提供多种引脚配置，包括 SOIC150-MIL、SOIC208-MIL、PDIP300-MIL 和 WSON6X5-MM 等封装类型。每种封装类型都提供了不同的引脚布局和功能。 **功能描述** 华邦 W25x Serial Flash 存储器提供了灵活的存储解决方案，适用于代码下载应用程序，以及存储语音、文本和数据。该系列产品支持 SPI 操作模式，能够高速传输数据。 **SPI 操作模式** 华邦 W25x Serial Flash 存储器支持 SPI 操作模式，能够高速传输数据。SPI 操作模式包括单工模式和双工模式，能够满足不同的应用需求。 **写保护功能** 华邦 W25x Serial Flash 存储器提供了写保护功能，能够保护存储器中的数据。写保护功能通过设置写保护位来实现，能够防止意外的数据写入。 **状态寄存器** 华邦 W25x Serial Flash 存储器提供了状态寄存器，能够存储存储器的状态信息。状态寄存器包括 BUSY、Write Enable Latch、Block Protect Bits、Top/Bottom Block Protect 等寄存器位。 **控制和状态寄存器** 华邦 W25x Serial Flash 存储器提供了控制和状态寄存器，能够控制存储器的操作状态。控制和状态寄存器包括 STATUS REGISTER、CONTROL REGISTER 等寄存器。 **应用场景** 华邦 W25x Serial Flash 存储器广泛应用于各种电子产品，包括智能手机、笔记本电脑、数字相机、MP3 播放器等。该系列产品的灵活性和性能使其非常适合这些应用场景。

W25X10, W25X20, W25X40, W25X80

- 8 -

8. BLOCK DIAGRAM

Figure 2. W25X10, W25X20, W25X40 and W25X80 Block Diagram

W25X10, W25X20, W25X40, W25X80

Publication Release Date: September 22, 2006

- 9 - Preliminary - Revision I

9. FUNCTIONAL DESCRIPTION

9.1 SPI OPERATIONS

9.1.1 SPI Modes

The W25X10/20/40/80 is accessed through an SPI compatible bus consisting of four signals: Serial

Clock (CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI

bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data

is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the

CLK signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of

the CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.

9.1.2 Dual Output SPI

The W25X10/20/40/80 supports Dual output operation when using the "Fast Read with Dual Output"

(3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice

the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from

Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM

for execution. The Dual output feature simply allows the SPI input pin to also serve as an output

during this instruction. All other operations use the standard SPI interface with single output signal.

9.1.3 Hold Function

The /HOLD signal allows the W25X10/20/40/80 operation to be paused while it is actively selected

(when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals

are shared with other devices. For example, consider if the page buffer was only partially written when

a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of

the instruction and the data in the buffer so programming can resume where it left off once the bus is

available again.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will

activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition

will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will terminate after the next falling edge of CLK.

During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data

Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept

active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the

device.

W25X10, W25X20, W25X40, W25X80

- 10 -

9.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern the

W25X10/20/40/80 provides several means to protect data from inadvertent writes.

9.2.1 Write Protect Features

• Device resets when VCC is below threshold.

• Time delay write disable after Power-up.

• Write enable/disable instructions.

• Automatic write disable after program and erase.

• Software write protection using Status Register.

• Hardware write protection using Status Register and /WP pin.

• Write Protection using Power-down instruction.

Upon power-up or at power-down the W25X10/20/40/80 will maintain a reset condition while VCC is

below the threshold value of V

WI, (See Power-up Timing and Voltage Levels and Figure 20). While

reset, all operations are disabled and no instructions are recognized. During power-up and after the

VCC voltage exceeds V

WI, all program and erase related instructions are further disabled for a time

delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase

and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC

supply level at power-up until the VCC-min level and t

VSL time delay is reached. If needed a pull-up

resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register

Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page

Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically

cleared to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status

with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under

hardware control. See Status Register for further information.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are

ignored except for the Release Power-down instruction.

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