![](https://csdnimg.cn/release/download_crawler_static/12346698/bgb.jpg)
(AP TO BB)
BRIEFLY SWITCHED TO PD TO CHECK STATE.
PIN J31 (UART7_RXD) SHOULD BE
STUFF R0911 FOR ANALOG PROX.
NOSTUFF R0911 FOR DOPPLER PROX.
I2C PROBE POINTSBUTTON PULL-UP RESISTORS
APN:335S0946
ANTI-ROLLBACK EEPROM
.
MAUI - GPIO & SERIAL INTERFACES
128kbit
8 OF 59
9 OF 49
A.0.0
051-1902
PP1V8
I2C2_AP_SCL
I2C1_AP_SCL
I2C1_AP_SDA
PP1V8
I2C2_AP_SDA
I2C_SEP_BI_EEPROM_SDA
AP_TO_PMU_SOCHOT1_L
PMU_TO_AP_SOCHOT0_R_L
PP1V8
PP1V8_ALWAYS
PMU_TO_AP_SOCHOT0_L
SPI_AP_TO_CODEC_SCLK
I2C2_AP_SDA
I2C1_AP_SDA
I2C0_AP_SDA
I2C2_AP_SCL
I2C1_AP_SCL
I2C0_AP_SCL
SPI_AP_TO_MESA_MOSI
SPI_AP_TO_MESA_SCLK_R
AP_TO_NAND_SYS_CLK_R
AP_TO_NAND_SYS_CLK
SPI_TOUCH_TO_AP_MISO
SPI_AP_TO_TOUCH_CS_L
MESA_TO_AP_INT
SPI_AP_TO_TOUCH_SCLK
UART_AP_TO_BT_TXD
CAM_EXT_LDO_EN
AP_TO_HP_HS4_CTRL
TRISTAR_TO_AP_INT
UART_AP_DEBUG_TXD
BOARD_ID0
BOOT_CONFIG2
AP_TO_BB_MESA_UP_L
DFU_STATUS
AP_TO_HP_HS3_CTRL
AP_TO_BB_PCIE_DEV_WAKE
AP_TO_SPEAKERAMP_RESET_L
AP_TO_SPEAKERAMP_STAYIN_ALIVE
BUTTON_VOL_UP_L
I2S_AP_TO_BT_LRCLK
UART_AP_TO_WLAN_TXD
FORCE_DFU
BUTTON_RINGER_A
I2S_AP_TO_CODEC_ASP_LRCLK
I2S_AP_TO_BB_LRCLK
I2S_AP_TO_CODEC_ASP_DOUT
I2S_CODEC_TO_AP_OWL_XSP_DIN
SPI_MESA_TO_AP_MISO
SPI_AP_TO_TOUCH_MOSI
I2S_AP_TO_ARC_MCLK_R
I2S_AP_TO_BT_BCLK
I2S_AP_TO_CODEC_XSP_DOUT
I2S_BT_TO_AP_DIN
I2S_AP_TO_BB_BCLK
I2S_CODEC_TO_AP_ASP_DIN
I2S_AP_TO_CODEC_ASP_BCLK
ALS_TO_AP_INT_L
I2S_AP_TO_BB_DOUT
I2S_BB_TO_AP_DIN
I2S_AP_TO_CODEC_MSP_BCLK
I2S_CODEC_TO_AP_MSP_DIN
I2S_AP_TO_CODEC_MSP_DOUT
I2S_AP_TO_CODEC_MSP_LRCLK
BOARD_ID2
BOARD_ID1
SPI_CODEC_TO_AP_MISO
SPI_AP_TO_CODEC_MOSI
SPI_AP_TO_CODEC_CS_L
I2S_AP_TO_BT_DOUT
I2S_AP_TO_SPEAKERAMP_MCLK_R
I2S_AP_OWL_TO_CODEC_XSP_LRCLK
I2S_AP_OWL_TO_CODEC_XSP_BCLK
I2S_AP_TO_CODEC_MCLK_R
SPI_AP_TO_TOUCH_SCLK_R
I2C_SEP_TO_EEPROM_SCL
AP_TO_TOUCH_CLK32K_RESET_L
BUTTON_VOL_DOWN_L
SPEAKERAMP_TO_AP_INT_L
UART_BT_TO_AP_RXD
BOARD_REV0
AP_TO_BB_RADIO_ON_L
BOOT_CONFIG1
BB_TO_AP_RESET_DETECT_L
AP_TO_STOCKHOLM_DEV_WAKE
BOARD_ID3
NC_AP_TO_STOCKHOLM_SIM_SEL
AP_TO_LCM_RESET_L
AP_TO_LED_DRIVER_EN
AP_TO_TOUCH_RESET_L
AP_TO_BT_WAKE
AP_TO_BB_RESET_L
PCIE_AP_TO_WLAN_DEV_WAKE
PROX_SELECT
UART_STOCKHOLM_TO_AP_RXD
SWI_AP_BI_TIGRIS
UART_WLAN_TO_AP_RXD
UART_AP_TO_STOCKHOLM_TXD
UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD
UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L
UART_STOCKHOLM_TO_AP_CTS_L
UART_AP_TO_STOCKHOLM_RTS_L
UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L
UART_AP_DEBUG_RXD
PMU_TO_AP_IRQ_L
SPI_AP_TO_MESA_SCLK
I2S_AP_TO_CODEC_MCLK
I2S_AP_TO_SPEAKERAMP_MCLK
I2S_AP_TO_ARC_MCLK
BUTTON_HOLD_KEY_L
I2C_SEP_TO_EEPROM_SCL
PP1V8
I2C_SEP_BI_EEPROM_SDA
PP1V8
BUTTON_RINGER_A
PP1V8_ALWAYS
BUTTON_MENU_KEY_L
PP1V8_SDRAM
I2C0_AP_SCL
I2C0_AP_SDA
LCM_TO_OWL_BSYNC
BOOT_CONFIG0
MAMBA_EXT_LDO_EN
BOARD_ID4
CODEC_TO_AP_PMU_INT_L
BOARD_REV1
BOARD_REV2
BOARD_REV3
AP_TO_NAND_FW_STRAP
TOUCH_TO_AP_INT_L
AP_TO_BB_COREDUMP
BB_IPC_GPIO
BB_TO_AP_GPS_TIME_MARK
ARC_TO_AP_INT_L
AP_TO_ARC_RESET_L
AP_TO_ARC_STAYIN_ALIVE
SYNC_DATE=N/A
SOC:SERIAL & GPIO
SYNC_MASTER=N/A
33
ROOM=SOC
01005
2
1
1.00K
1%
1/32W
MF
R0900
1
2
MF
5%
ROOM=SOC
01005
1/32W
2.2K
R0901
2
1
MF
5%
1/32W
10K
01005
ROOM=SOC
R0941
ROOM=SOC
SM
P3MM-NSM
1
PP0905
ROOM=SOC
SM
P3MM-NSM
1
PP0903
ROOM=SOC
SM
P3MM-NSM
1
PP0901
ROOM=SOC
P3MM-NSM
1
SM
PP0904
SM
1
P3MM-NSM
ROOM=SOC
PP0902
SM
1
PP0900
P3MM-NSM
ROOM=SOC
21
AM2
AM1
M32
ROOM=SOC
D35
V3
AC4
AA3
Y2
AA2
F31
F34
E35
E33
M31
N32
V35
P33
AD3
AB2
AC3
AD4
W3
U2
AA4
Y4
AB4
Y3
AM24
R32
V32
P32
P31
R31
AM3
AN2
AN1
AP1
AM4
U32
U33
V34
T33
V33
M4
P1
L4
N3
M3
P34
N34
M33
N35
R34
L31
AG4
AH1
E31
H31
H34
U0600
CRITICAL
SC58980B0B-A040
FCMSP
MAUI-2GB-25NM-DDR-H
AJ1
J32
J31
AE2
AF1
T32
K33
J35
J34
J33
R2
R3
P3
N4
AP22
AP23
AR20
AT23
L32
L33
K32
K31
AE4
AE3
AF3
AF2
AE1
AP10
AP9
AP8
AT5
AP7
AR6
AT4
AT3
AP6
AR4
AR3
AR2
AP5
AP4
AN4
AP3
AK1
AJ4
AJ3
AJ2
AH4
AH3
AH2
N1
L3
K3
L2
J4
K2
J3
K1
H4
J1
G3
H3
F2
F3
E2
F1
D1
D2
C1
U0600
FCMSP
SC58980B0B-A040
MAUI-2GB-25NM-DDR-H
CRITICAL
ROOM=SOC
OMIT_TABLE
2
1
R0950
DEFAULT_RESISTOR_191000OHM_2_1
01005
191K
1%
1/32W
MF
ROOM=SOC
P2MM-NSM
SM
PP0906
1
ROOM=SOC
28
R0911
ANALOG_PROX
2
1
1.00K
01005
ROOM=SOC
1/32W
5%
MF
21
R0960
01005
0%
0.00
1/32W
ROOM=SOC
MF
1
1/32W
1%
ROOM=SOC
R0905
1.33K
01005
2
MF
R0904
1.33K
1/32W
1%
2
ROOM=SOC
MF
01005
1
24
24
24
24
29
31
31
21
R0945
MF
0%
0.00
1/32W
01005
ROOM=SOC
13
30 16
24
24
9
24 9
24 9
26 25 24
26 25 24
26 25 24
26 25 24
26
26
26
25
26
24
21
R0921
01005
MF
ROOM=SOC
1/32W
1%
33.2
33
2
1
R0952
220K
ROOM=SOC
01005
MF
1/32W
5%
2
1
R0951
1/32W
100K
5%
MF
01005
ROOM=SOC
21
01005
0%
MF1/32W
0.00
ROOM=SOC
R0930
29
33
33
3
33 32
16 8
33 29 9
33
16
29
33
33
33
24 16
16
16
2
0.00
01005
1
ROOM=SOC
0% MF
1/32W
R0940
10K
R0910
ROOM=SOC
2
01005
MF
1/32W
5%
1
NOSTUFF
8
8
8
8
1/32W
2
1
R0907
5%
MF
01005
ROOM=SOC
2.2K
1/32W
ROOM=SOC
2
1
R0906
MF
01005
5%
2.2K
B2 A1
A2B1
U0900
CRITICAL
WLCSP
M34128-FCS6_P/T
ROOM=SOC
28
28
28
28
29
29
29
24
24
24
24
20
33
33
33
33
33
33
33
33
30
30
33
33
33
33
33
33
33
33
33
33
33
33
33 30
33
30
13
33 3
33 3
29
28
33
25
25
25
33 32 16
33 32 16
33
3
3
3
3
3
3
3
3
3
3
3
33
22
17 9
1/32W
5%
MF
2
01005
ROOM=SOC
2.2K
R0902
1
ROOM=SOC
1
5%
1/32W
MF
2.2K
R0903
01005
2
33 27 16 8
33 27 16 8
33 30 26 25 17 8
33 30 26 25 17 8
29 20 8
29 20 8
2
1
C0900
6.3V
1.0UF
0201-1
X5R
20%
ROOM=SOC
21
R0922
01005
MF
1%
ROOM=SOC
1/32W
33.2
ROOM=SOC
01005
10K
1/32W
5%
R0909
1
MF
2
21
R0920
MF
ROOM=SOC
01005
1%
33.2
1/32W
33 29
2120 17 14 13 12 9 8 7 6 5 3
33 29
2120 17 14 13 12 9 8 7 6 5 3
33 29
2120 17 14 13 12 9 8 7 6 5 3
17 15 12 8
29 20 8
33 30 26 25 17 8
33 27 16 8
29 20 8
33 30 26 25 17 8
33 27 16 8
33 32 16 9
33
29
21
20 17 14 13 12 9
8 7 6 5 3
33 29
21
20 17 14 13 12 9 8 7 6 5 3
33 32 16 8
17 15 12 8
33 28 16 9
33 31 30 27 24 16 15 14 12
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
PP
PP
PP
PP
PP
PP
OUT
SYM 6 OF 14
CPU_ACTIVE_STATUS
CLK32K_OUT
NAND_SYS_CLK
SOCHOT0
SOCHOT1
SEP_SPI0_SCLK
SEP_SPI0_MISO
SEP_SPI0_MOSI
SEP_I2C_SCL
SEP_I2C_SDA
SEP_GPIO0
SEP_GPIO1
SPI2_SCLK
I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S2_MCK
I2S1_DOUT
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
I2S4_LRCK
I2S4_DOUT
I2S4_DIN
I2S4_BCLK
I2S3_DIN
I2S3_DOUT
I2S3_MCK
I2S2_BCLK
I2S2_DIN
I2S3_BCLK
I2S1_LRCK
I2S1_DIN
I2S0_DOUT
I2S1_BCLK
I2S1_MCK
I2C0_SCL
I2C1_SCL
I2C2_SCL
I2C0_SDA
SPI2_SSIN
SPI2_MOSI
SPI2_MISO
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
I2C1_SDA
I2S0_DIN
I2S2_DOUT
I2C2_SDA
I2S4_MCK
I2S3_LRCK
I2S2_LRCK
SYM 5 OF 14
GPIO_13
GPIO_22
TMR32_PWM0
GPIO_1
GPIO_26
UART0_RXD
UART4_RTS*
UART4_CTS*
UART3_RTS*
UART3_CTS*
UART2_RTS*
UART2_CTS*
UART1_RTS*
UART1_CTS*
UART6_TXD
UART6_RXD
TMR32_PWM2
TMR32_PWM1
UART3_TXD
UART4_RXD
UART4_TXD
UART5_RTXD
UART3_RXD
UART7_RXD
UART7_TXD
GPIO_9
GPIO_8
GPIO_7
GPIO_11
GPIO_10
GPIO_12
GPIO_14
GPIO_18
GPIO_19
GPIO_17
GPIO_16
GPIO_15
GPIO_20
GPIO_21
GPIO_23
GPIO_24
GPIO_25
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
UART2_RXD
UART2_TXD
UART1_TXD
UART1_RXD
UART0_TXD
GPIO_6
GPIO_5
GPIO_4
GPIO_3
GPIO_2
GPIO_0
PP
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
NC
NC
NC
OUT
IN
OUT
OUT
OUT
OUT
IN
NC
OUT
OUT
OUT
NC
NC
NC
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
BI
BI
OUT
NC
NC
NC
SDA
SCL
VCCVSS
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
NC
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
OUT
BI
OUT
BI
OUT
BI
NC
NC
NC