ACTEL ProASIC3 FPGA技术规格与特性解析

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"ACTEL ProASIC3是一款由Microsemi Actel公司生产的高性能、低功耗、可编程闪存FPGA（现场可编程门阵列），适用于各种嵌入式系统和工业应用。该器件提供了从15千系统门到1百万系统门的不同容量选择，以及高达144千比特的真正双端口SRAM，并支持多达300个用户I/O接口。" ACTEL ProASIC3的主要特点和优势包括： 1. 高容量：该系列FPGA的逻辑容量范围广泛，从15千系统门到100万系统门不等，能满足不同复杂度的设计需求。同时，它还配备了最多144千比特的双端口SRAM，这对于需要高速缓存或存储大量数据的应用非常有用。 2. 可编程闪存技术：基于130纳米7层金属（包含6层铜）的闪存CMOS工艺，ProASIC3支持在电源开启时立即运行（Live at Power-Up, LAPU）的Level 0功能，提供单芯片解决方案，并能在断电后保持编程设计不变。 3. 高性能：器件可实现350MHz的系统性能，支持3.3V、66MHz的64位PCI接口，适合高性能计算和通信应用。 4. 在系统编程（ISP）与安全性：通过JTAG（符合IEEE 1532标准）接口，ProASIC3支持安全的在系统编程，使用128位高级加密标准（AES）解密（除带有ARM支持的ProASIC3设备外）。此外，还提供了FlashLock功能，用于保护FPGA内容的安全。 5. 低功耗：具备核心电压控制以降低功耗，支持1.5V的系统，适应低功耗要求。同时，采用低阻抗闪存开关，进一步优化了能耗。 6. 高性能路由层次：采用分段化、分层化的路由结构和时钟架构，提高了信号传输速度和系统的整体性能。 7. 先进的I/O特性：支持700Mbps的DDR和LVDS兼容I/O（A3P250及以上型号），可以进行1.5V、1.8V、2.5V和3.3V的混合电压操作，符合JESD8-B标准，允许I/O在宽范围的电源电压下工作，增强了灵活性和兼容性。 ACTEL ProASIC3系列是专为那些需要高集成度、高性能、低功耗和安全性的嵌入式系统设计者设计的。其广泛的功能和特性使其在通信、工业控制、军事、航空航天和消费电子等领域具有广泛应用。

ProASIC3 DC and Switching Characteristics

2-2 Revision 9

Table 2-2 • Recommended Operating Conditions

1,2

Symbol Parameter Commercial Industrial Units

Ambient temperature 0 to +70 -40 to +85 °C

Junction temperature 0 to 85 -40 to 100

VCC

1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.0 to 3.6 3.0 to 3.6 V

Operation

0 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.4 to 1.6 1.4 to 1.6 V

VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 2.7 to 3.6 2.7 to 3.6 V

3.3 V wide range DC supply voltage

3.0 to 3.6 3.0 to 3.6 V

LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-18 on page 2-19. VMV and VCCI should be at the same voltage within a given I/O bank.

4. V

PUMP

can be left floating during operation (not programming mode).

5. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature

Product

Grade

Programmin

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature T

STG

(°C)

Maximum Operating

Junction Temperature T

(°C)

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3 Flash Family FPGAs

Revision 9 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC

3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up

behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The V

activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for

information on clock and lock recovery.

Table 2-4 • Overshoot and Undershoot Limits

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/

Undershoot

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3 Flash Family FPGAs

Revision 9 2-5

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

= Junction Temperature = ΔT + T

EQ 1

where:

= Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ

* P

= Junction-to-ambient of the package. θ

numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ

and the junction-to-ambient air thermal resistivity is

. The thermal characteristics for θ

are shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

EQ 2

Maximum Power Allowed

Max. junction temp. (°C) Max. ambient temp. (°C)–

(°C/W)

---------------------------------------------------------------------------------------------------------------------------------------

100°C70°C–

20.5°C/W

------------------------------------ 1.463 W

===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θ

UnitsStill Air 200 ft./min. 500 ft./min.

Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W

A3P060 132 0.3 21.2 16.6 15.0 C/W

A3P125 132 0.2 21.1 16.5 14.9 C/W

A3P250 132 0.1 21.0 16.4 14.8 C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W

Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W

PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W

See note* 256 3.8 26.6 22.8 21.5 C/W

See note* 484 3.2 20.5 17.0 15.9 C/W

A3P1000 144 6.3 31.6 26.2 24.2 C/W

A3P1000 256 6.6 28.1 24.4 22.7 C/W

A3P1000 484 8.0 23.3 19.0 16.7 C/W

* This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information

will be available in future revisions of the datasheet.

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