EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *E 4
Inrush Current Consideration and Power
Supply Design
When the USB 3.0 Super Speed PHY is enabled for the
first time, or a reset event; an initial inrush current is
expected on the 1.2 V U3RXVDDQ and U3TXVDDQ
supplies for ~10 us. The magnitude of this current can be
as high as 800 mA. In order that this inrush current does
not cause the common 1.2 V supply to droop to
unacceptable levels, care must be taken in the design of
the power supply network for these supplies.
If the same 1.2 V supply is also used for the VDD core
supply, care must be taken to insure that the level on this
supply does not fall too low, as this has the potential to trip
the on-chip power-on reset (POR) circuit that will reset the
entire chip. The POR circuit can fire if the 1.2-V core VDD
voltage falls down to less than 0.83 V for more than
200 ns. The 1.2-V power network must be designed such
that the VDD does not drop below 0.83 V when an inrush
event occurs. Proper combination of decoupling capacitors
(as specified in the datasheet), inductor chokes and
regulator output impedance are required to make this
possible.
The following example waveforms show the inrush current
(Figure 4) and resultant drop in VDD levels (Figure 5)
when the current spike occurs. The results were obtained
from a non-optimized power supply design using
TPS76801QD power regulator, 2.2-uF decoupling caps,
and chokes as shown in Figure 3.
Figure 3. Non-optimized Power Supply Design
U3RXVDDQ
U3TXVDDQ
VDD
FX3
0.1µF 2.2µF
0.1µF 2.2µF
0.1µF 2.2µF
Lchoke
Lchoke
Lchoke
Regulator
TPS76801QD
V1P2
Figure 4. Inrush Current (80 mV/0.1 Ω = 800 mA)
Figure 5. 1.2-V Power Domain Voltage Drop (200 mV)
In contrast, an optimized power design shown in Figure 6
below designed using the same regulator (TPS76801QD),
with the modification of using a 22-uF decoupling
capacitor and removing the choke from VDD supply,
shows a reduction in the inrush (Figure 7) and an
improvement in the power supply drop (Figure 8).
Figure 6. Optimized Power Supply Design
U3RXVDDQ
U3TXVDDQ
VDD
FX3
0.1µF 22µF
0.1µF 22µF
0.1µF 22µF
Lchoke
Lchoke
Regulator
TPS76801QD
V1P2
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