EZ-USB FX3 USB3.0硬件设计指南与要点

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本篇文档是Cypress公司关于EZ-USB FX3™硬件设计指南和线路图检查清单（Document No. 001-70707 Rev.*E），主要针对Cypress的USB 3.0控制器CYUSB3014进行深入讨论。该指南旨在为开发者提供推荐的最佳实践，帮助他们在设计USB 3.0设备时考虑关键要素。 1. **介绍**：文档首先介绍了EZ-USB FX3，一款高度集成且灵活的USB 3.0外围控制器，允许开发人员轻松将USB 3.0功能添加到任何系统中。它强调了新一代接口的速度和性能优势。 2. **电源系统**：设计者需要关注系统的供电需求，包括设备的稳定供电、电压降和电源去耦，以确保在高速数据传输时的可靠性和稳定性。 3. **功率模式与电流管理**：文档涉及如何处理设备启动时的上电冲击电流，并对电源设计进行优化，以适应USB 3.0的功耗特性。 4. **时钟管理**：为了保证数据通信的精确性，时钟的选择、配置以及与主时钟源的同步都是至关重要的。文档涵盖晶体振荡器、内部时钟、看门狗定时器等。 5. **接口设计**：指南详细讲解了GPIF II、I2C、LPP（低性能外设）、JTAG、I2S、SPI和UART等接口的使用方法，确保设备能与其他电路板上的模块有效通信。 6. **引导和启动流程**：描述了设备的启动流程和可能的引导策略，确保系统能够在正确的时间进入工作状态。 7. **电磁兼容性和静电防护**：设计者需要遵循EMI（电磁干扰）和ESD（静电放电）标准，以减少对周边电子设备的潜在影响。 8. **物理尺寸与电气设计**：包含了FX3设备封装尺寸信息，以及USB 3.0 SuperSpeed的具体设计指导，如信号线迹宽度、间距等。 9. **PCB布局建议**：附录A提供了实用的PCB设计技巧，帮助设计师实现高效的电路布局，以满足USB 3.0的信号完整性要求。总结起来，这份文档为EZ-USB FX3的硬件开发人员提供了全面的设计指导，涵盖了从电源管理、接口配置到电气规范的各个关键环节，确保设计出符合USB 3.0标准、性能卓越的外设设备。对于想要利用这款控制器开发USB 3.0产品的工程师来说，这是一份不可或缺的参考资料。

EZ-USB

FX3™ Hardware Design Guidelines and Schematic Checklist

www.cypress.com Document No. 001-70707 Rev. *E 4

Inrush Current Consideration and Power

Supply Design

When the USB 3.0 Super Speed PHY is enabled for the

first time, or a reset event; an initial inrush current is

expected on the 1.2 V U3RXVDDQ and U3TXVDDQ

supplies for ~10 us. The magnitude of this current can be

as high as 800 mA. In order that this inrush current does

not cause the common 1.2 V supply to droop to

unacceptable levels, care must be taken in the design of

the power supply network for these supplies.

If the same 1.2 V supply is also used for the VDD core

supply, care must be taken to insure that the level on this

supply does not fall too low, as this has the potential to trip

the on-chip power-on reset (POR) circuit that will reset the

entire chip. The POR circuit can fire if the 1.2-V core VDD

voltage falls down to less than 0.83 V for more than

200 ns. The 1.2-V power network must be designed such

that the VDD does not drop below 0.83 V when an inrush

event occurs. Proper combination of decoupling capacitors

(as specified in the datasheet), inductor chokes and

regulator output impedance are required to make this

possible.

The following example waveforms show the inrush current

(Figure 4) and resultant drop in VDD levels (Figure 5)

when the current spike occurs. The results were obtained

from a non-optimized power supply design using

TPS76801QD power regulator, 2.2-uF decoupling caps,

and chokes as shown in Figure 3.

Figure 3. Non-optimized Power Supply Design

U3RXVDDQ

U3TXVDDQ

VDD

FX3

0.1µF 2.2µF

Lchoke

Regulator

TPS76801QD

V1P2

Figure 4. Inrush Current (80 mV/0.1 Ω = 800 mA)

Figure 5. 1.2-V Power Domain Voltage Drop (200 mV)

In contrast, an optimized power design shown in Figure 6

below designed using the same regulator (TPS76801QD),

with the modification of using a 22-uF decoupling

capacitor and removing the choke from VDD supply,

shows a reduction in the inrush (Figure 7) and an

improvement in the power supply drop (Figure 8).

Figure 6. Optimized Power Supply Design

U3RXVDDQ

U3TXVDDQ

VDD

FX3

0.1µF 22µF

Lchoke

Regulator

TPS76801QD

V1P2

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