深入解析UVM验证方法学与Testbench构建

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"UVM验证方法学深入讲解，包含多种实例，教授如何利用UVM构建Testbench模块，由MENTOR GRAPHICS提供的一份详细的在线烹饪书，涵盖了从Testbench架构到组件、代理、阶段管理、工厂机制、系统Verilog包、与DUT接口的连接、参数化测试以及配置等多个方面。" 在UVM（Universal Verification Methodology）验证方法学中，它提供了一套标准化的框架和库，用于构建和复用可扩展的验证环境。UVM的核心理念是基于组件的验证，它将验证环境划分为多个可重用的部分，如Testbench、组件、代理、驱动、监控器等，从而提高验证效率和代码质量。 1. **Testbench架构**：Testbench是验证环境的基石，它模拟了被验证设计（DUT，Design Under Test）运行的环境。Testbench通常包括激励生成器、响应分析器、 scoreboard和其他辅助组件。`Testbench/Overview`介绍了Testbench的基本结构，`Testbench/Build`则讲解了如何构建Testbench，而`Testbench/Blocklevel`和`Testbench/IntegrationLevel`分别针对模块级和系统级集成的Testbench设计进行了探讨。 2. **组件(Component)**：UVM组件是构建验证环境的基本单元，它们可以是简单的数据处理模块，也可以是复杂的测试序列生成器。`Component`章节详细阐述了组件的创建、配置和连接。 3. **代理(Agent)**：代理是连接DUT接口和Testbench的桥梁，它包括驱动（Driver）、监控器（Monitor）和收发机（Sequencer）。`Agent`部分解释了如何定义和使用这些组件来实现有效的通信。 4. **阶段管理(Phasing)**：UVM的时序模型允许在不同验证阶段执行不同的任务，如初始化、运行测试、报告结果等。`Phasing/Overview`和`Using Factory Overrides`讲述了如何管理和定制这些验证阶段。 5. **工厂(Factory)**：工厂机制允许动态地创建和配置UVM对象，提供了灵活的类实例化和类型映射。`Factory`和`Using Factory Overrides`部分深入讲解了这一关键特性。 6. **系统Verilog包(SystemVerilog Packages)**：UVM基于SystemVerilog语言，系统Verilog包定义了UVM的基础类和接口。`SystemVerilogPackages`章节解释了如何使用和扩展这些包。 7. **与DUT接口的连接(Connecting to DUT Interfaces)**：这部分涵盖了如何将Testbench组件与DUT接口进行连接，包括`Connect/DutInterface`、`SVCreationOrder`和`Connect/SystemVerilogTechniques`等，讨论了接口的虚拟化和连接策略。 8. **参数化测试(Parameterized Tests)**：`ParameterizedTests`章节介绍如何创建能够适应不同输入参数的测试用例。 9. **虚拟接口(Virtual Interface)**：`VirtualInterface`相关章节讲解了如何使用虚拟接口来传递和处理协议数据，以及如何配置和管理这些接口。 10. **配置(Configure)**：配置管理是UVM的重要特性，它允许在运行时对组件进行定制。`Configuring a Test Environment`章节详细介绍了配置数据库（Config DB）和配置过程。这份文档通过实例和详细说明，帮助读者理解并掌握UVM验证方法学的各个方面，是学习和应用UVM进行SoC验证的宝贵参考资料。无论是初学者还是经验丰富的验证工程师，都能从中受益。

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Testbench/Build

the UVM•phases run to completion before control is passed back to the testbench module.

The Test Is The Starting Point For The Build Process

The build process for an UVM•testbench starts from the test class and works top-down.•The test class build method is the

first to be called during the build phase and what the test method sets up•determines what gets built in an UVM

testbench.•The function of the•tests build method is to:

€ Set up any factory overrides so that configuration objects or component objects are created as derived types

€ Create and configure the configuration objects required by the various sub-components

€ Assign any virtual interface handles•put into configuration space by the testbench module

€ Build•up a nested env configuration object which is then set into configuration space

€ Build the next level down in the testbench hierarchy, usually the top-level env

For a given design verification environment most of the work done in the build method will be the same for all the tests,

so it is recommended that a test base class is created which can be easily extended for each of the test cases.

To help explain how the test build process works, a block level verification environment will be referred to. This

example is an environment for an SPI•master interface DUT and it contains two agents, one for its APB•bus interface and

one for its SPI interface. A detailed account of the build and connect processes for this example can be found in the

Block Level Testbench Example•article.

Testbench/Build

Assigning Virtual Interfaces From The Configuration Space

Before the UVM run_test() method is called, the links to the signals on the top level I/O boundary of the DUT should

have been made by connecting them to SystemVerilog interfaces and then a handle to each interface should have been

assigned to a virtual interface handle which is passed in to the test using uvm_config_db::set. See the article on virtual

interfaces for more information on this topic.

In the test build method, these virtual interface references need to be assigned to the virtual interface handles inside the

relevant component configuration objects. Then, individual components access the virtual interface handle inside their

configuration object in order to drive or monitor DUT signals. In order to keep components modular and reusable drivers

and monitors should not get their virtual interface pointers directly from configuration space, only from their

configuration object. The test class is the correct place to ensure that the virtual interfaces are assigned to the right

verification components via their configuration objects.

The following code shows how the the SPI testbench example uses the uvm_config_db::get method to make virtual

interface assignments to the virtual interface handle in the apb_agents configuration object:

// The build method from before, adding the apb agent virtual interface assignment

// Build the env, create the env configuration

// including any sub configurations and assigning virtural interfaces

function void spi_test_base::build_phase( uvm_phase phase );

// Create env configuration object

m_env_cfg = spi_env_config::type_id::create("m_env_cfg");

// Call function to configure the env

configure_env(m_env_cfg);

// Create apb agent configuration object

m_apb_cfg = apb_agent_config::type_id::create("m_apb_cfg");

// Call function to configure the apb_agent

configure_apb_agent(m_apb_cfg);

// Adding the apb virtual interface:

if( !uvm_config_db #( virtual apb3_if )::get(this, "" , "APB_vif",m_apb_cfg.APB) ) `uvm_error(...)

// More to follow

endfunction: build_phase

Nesting Sub-Component Configuration Objects

Configuration objects are passed to sub-components via the UVM component configuration space from the test. They

can be passed individually, using the path argument in the uvm_config_db::set method to control which components can

access the objects. However a common requirement is that intermediate components also need to do some local

configuration.

Therefore, an effective way to approach the passing of configuration objects through a testbench hierarchy is to nest the

configuration objects inside each other in a way that reflects the hierarchy itself. At each intermediate level in the

testbench, the configuration object for that level is unpacked and then its sub-configuration objects are re-configured (if

necessary) and then passed to the relevant components using uvm_config_db::set.

Following the SPI block level envrionment example, each of the agents will have a separate configuration object. The

envs configuration object will have a handle for each of the agents configuration object. In the test, all of the

configuration objects will be constructed and configured from the test case viewpoint, then the agent configuration object

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