AD9371用户指南：软件定义射频收发器集成

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"ad9371用户指南UG992" ADI公司的AD9371是一款集成的双射频收发器，具有观测路径功能，适用于软件定义无线电（SDR）应用。用户指南UG-992是为系统工程师和软件开发者提供的重要参考资料，旨在详细介绍如何使用AD9371及其API函数。 1. **系统概述** 系统概述部分首先阐述了AD9371设备的能力，为用户提供了设备功能的整体认识。这一部分包括了对所有子系统和功能的简介，如内部的块图和接口描述。AD9371集成了高性能的数字信号处理能力，支持多种无线通信标准，能够实现灵活的发射和接收功能。 2. **系统架构描述** 在这部分，用户将了解到软件设计的方法，特别是通过应用编程接口（API）进行设计的策略。API允许开发者控制AD9371的各种功能，如频率合成、调制解调、数据速率设置等。此外，还包括了开发设备上代码所需的详细信息，如寄存器映射、中断处理和错误管理。 3. **软件集成** 这一章节指导开发者如何将自定义代码与AD9371硬件进行集成。涵盖了开发环境的设置、驱动程序安装、编译工具链的使用以及调试技巧。此外，还可能包含示例代码和库函数，帮助开发者快速理解和启动项目。 4. **硬件接口和配置** AD9371通过各种接口与外部系统通信，如SPI、I2C、JTAG等。这部分详细解释了如何配置这些接口，以及如何通过它们来初始化和控制AD9371的各个模块。 5. **性能优化** 用户指南还会涵盖性能优化的策略，包括功耗管理、信号质量提升和系统级性能的调整。这些信息对于确保在满足特定应用场景需求的同时，达到最佳的能效比至关重要。 6. **故障排查与支持** 提供了故障排除指南，帮助用户解决在开发和运行过程中遇到的问题。同时，可能还包含了ADI公司提供的技术支持信息，如在线论坛、文档库和客户服务联系方式。 7. **安全性和合规性** 由于AD9371可能用于无线电通信，所以这部分会涉及到法规遵从性，如电磁兼容性（EMC）和射频（RF）安全标准，确保设备在合法范围内操作。通过深入理解AD9371用户指南UG992，开发者可以充分利用这款高集成度的射频收发器，创建出高效、灵活且符合标准的无线通信解决方案。这份指南是开发过程中的重要参考，能有效加速产品开发进程并保证系统的稳定性和可靠性。

UG-992 System Development User Guide

Rev. A | Page 16 of 307

Table 4 lists the timing specifications for the SPI bus. The

relationship between these parameters is shown in Figure 6.

This diagram shows a 3-wire SPI bus timing diagram with the

AD9371 returning a value of 0xD4 from Register 0x00A; the

timing parameters are marked. Note that this is a single-read

operation; therefore, the bus ready parameter after the data is

driven from the AD9371 (t

HZS

) is not shown in the diagram.

Table 4. SPI Bus Timing Constraint Values

Parameter Min Typ Max Description

20 ns

SCLK cycle time (clock period)

10 ns SCLK pulse width

3 ns CSB setup time to first SCLK rising edge

0 ns Last SCLK falling edge to CSB hold

3 ns SDIO data input setup time to SCLK

0 ns

SDIO data input hold time to SCLK

3 ns 8 ns SCLK falling edge to output data delay (3-wire or 4-wire mode)

HZM

Bus turnaround time after BBP drives the last address bit

HZS

3 ns t

Bus turnaround time after the AD9371 drives the last data bit (not shown in

Figure 6)

SDIO

CSB

DON’T CARE

SCLK

HZM

14652-006

R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 6. 3-Wire SPI Timing with Parameter Labels, SPI Read Operation

UG-992 System Development User Guide

Rev. A | Page 18 of 307

RECEIVERS (ADC) DATAPATH

The transport and link layers for JESD204B are performed in the

framers. The AD9371 has two JESD204B framers that multiplex

into four serial lanes. Samples from the main receivers are sent

to the first framer. Samples from the sniffer/observation receiver

are sent to the second framer. Each framer has its own SYNCB

signal. This allows the sniffer/observation JESD204B lanes to be

brought down for reconfiguration without interrupting the

main receiver lanes.

The two framers are capable of operating at different sample

rates. The higher sample rate must be a power of two multiples

of the lower sample rate (for example, 2×, 4×, or 8×). For example,

the two main receivers can be configured for a 122.88 MHz

sample rate into the framer, and a sniffer with a sample rate of

30.72 MHz can be connected to the second framer. There are

two options to make this work: oversample at the framer input

or bit repeat at the serializer output. Oversample mode repeats

sample values at the framer input of the slower rate, allowing all

the serializers to run at the same bit rate. Bit repeat mode repeats

each bit in the lane or lanes that carry the slower data as it exits

the serializer. Because this is after the 8-bit/10-bit encoding, it

appears as if the lane is running at a slower data rate than the

other lanes.

Both framers must share the four serializers. Each framer must

be configured for 0, 1, 2, or 4 lanes such that the two framers

combine for no more than 4 lanes. If one framer uses all 4 lanes,

then the other framer cannot be used.

Each framer has an ADC crossbar that can connect any ADC

to any framer input. The ADC crossbar for the main receiver

framer has an optional automatic channel selection feature to

automatically shift the Rx2 ADCs to Framer 0 and Framer 1. If

the framer is configured for only two inputs (M = 2), Rx1 is

disabled, and Rx2 is enabled, the ADCs for Rx2 must be connected

to the Framer 0 and Framer 1 inputs. The automatic channel

selection feature allows this shift without reconfiguring the

ADC crossbar.

Each framer is capable of generating a pseudorandom bit

sequence (PRBS) on the enabled lanes. After the PRBS is

enabled, errors can be injected. Enabling the PRBS generator

disables the normal JESD204B framing, and may cause the

SYNCB signal to deassert.

The serializers can be configured to adjust the amplitude and

preemphasis of the physical signal to help combat bit errors due

to various PCB trace lengths.

Supported Framer Link Parameters

The AD9371 supports a subset of possible JESD204B link

configurations. The number of ADCs and the number of

JESD204B lanes implemented in the silicon limit these

configurations.

Table 5. Static JESD204B Parameters

JESD204B Parameter AD9371 Value Description

S 1 Samples transmitted/single converter/frame cycle

N 16 Converter resolution

N’ 16 Total number of bits per sample

Number of control words/frame clock cycle/converter device

CS 0 Number of control bits/conversion sample

HD 0 … 1 High density mode (only M2L4 uses HD = 1)

K Variable, suggested: 32 Number of frames in 1 multiframe, (20 ≤ F × K ≤ 256), F × K must be a multiple of 4, K ≤ 32

Table 6. JESD204B Parameters Dependent on Number of Lanes and Number of ADCs

Number of ADCs (M) Number of Lanes (L) Number of Bytes in 1 Frame (F) (F = 2 × M/L)

2 1 4

2 2 2

4 1 8

4 2 4

4 4 2

System Development User Guide UG-992

Rev. A | Page 19 of 307

For a particular converter sample rate, not all combinations

listed in Table 6 are valid. For the JESD204B configuration

mode to be valid, the lane rate for that mode must be within the

614.4 Mbps to 6144 Mbps range. The lane rate is the serial bit

rate for one lane of the JESD204B link. Calculate the lane rate

using Equation 1.

Lane Rate = IQ Sample Rate × M × 16 bits ×

÷ L (1)

Serializer Configuration

The amplitude of the serializer is represented by a 5-bit number

that is not linearly weighted. Not all settings are unique, and not

all settings meet the JESD204B transmitter mask. The JESD204B

transmitter mask requires a differential amplitude greater than

360 mV and less than 770 mV. To meet the JESD204B transmitter

mask, it is recommended to set the serializer amplitude to a

decimal value between 18 to 26. The default amplitude is

22 mV p-p.

Table 7. Serializer Amplitude Settings That Meet the

JESD204B Transmitter Mask

Serializer Amplitude

(Decimal) Differential Amplitude (mV p-p)

18 400

19 440

20 480

21 520

22 (default) 560

23 600

24 640

25 680

26 720

The values shown in Table 7 are calculated values based on the

design. Measured values are slightly lower than the calculated

values. It is always recommended to verify the eye diagram in

the system after building a PCB to verify any layout related

performance differences.

The serializer preemphasis allows boosting the amplitude any

time the serial bit changes state. If bit transition does not occur,

the amplitude is deemphasized. Preemphasis helps open the eye

diagram for longer PCB traces or when the parasitic loading of

connectors has a noticeable effect. In most cases, to find the

best setting, a simulation or measuring the eye diagram with a

high speed scope at the receiver is recommended. The serializer

preemphasis is represented by a 3-bit number. The range in

differential amplitude can be seen in Table 8, and its effects are

shown in Figure 8.

Table 8. Preemphasis Amplitude Settings

Emphasis (Decimal) Differential Amplitude (mV p-p)

0 0

1 40

2 80

3 120

4 160

5 200

6 240

7 280

EMPHASIS = 7

EMPHASIS = 3

EMPHASIS = 0

500

–500

–300

–100

100

300

DIFFERENTIAL AMPLITUDE (mV)

TIME

14652-008

Figure 8. Serializer Preemphasis Measured on 3 Gbps Serial Data, Serializer

Another metric for the effect of the serializer preemphasis is

how much insertion loss each preemphasis setting can overcome.

Different PCBs have different insertion loss due to factors such

as different materials, stackups, and trace geometry. However,

the insertion loss can be measured with a network analyzer or

simulated to estimate how much loss a particular PCB has. Note

that the preemphasis gain has some dependency on the main

serializer amplitude setting.

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