TI-CDCE6214-Q1：超低功耗时钟发生器技术规格

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"TI-CDCE6214-Q1.pdf" TI的CDCE6214-Q1是一款专为汽车应用设计的超低功耗时钟发生器，它集成了一个PLL（锁相环路）和四个差分输出，以及两个输入和内部EEPROM。该器件提供了一流的性能和电源效率，适用于各种高速接口，如FPGA、Ethernet和PCIe。其主要特点包括： 1. 汽车级标准：CDCE6214-Q1满足温度等级2的要求，工作温度范围为-40°C至+105°C，确保在极端环境下稳定工作。 2. 高性能、低功耗分数NPLL：在整数模式下，它可以提供极低的RMS抖动和杂散，差分输出的典型抖动为350fs，最大600fs；LVCMOS输出的典型抖动为1.05ps，最大1.5ps。在分数模式下，这些值分别提高到1.7ps和2.0ps（差分输出），以及2.1ps和4.0ps（LVCMOS输出）。 3. 支持PCIe Gen1/2/3/4：这款时钟发生器兼容带SSC（频率调制）的PCIe Gen1/2/3/4以及不带SSC的Gen1/2/3/4/5，确保与多种高速数据传输接口的兼容性。 4. 内部VCO（压控振荡器）频率范围广泛：从2.335GHz到2.625GHz，提供了灵活的时钟源选择。 5. 低功耗：4个输出通道时典型功耗为65mA，单个输出通道则为23mA，有效降低了系统整体的能耗。 6. 多样化的输入选项：具有通用时钟输入和两个基准输入，支持差分交流耦合或LVCMOS信号，频率范围从10MHz到200MHz，同时还有10MHz至50MHz的晶振输入。 7. 弹性的输出时钟分配：4个通道分频器可以提供多达5个独特的输出频率，频率范围从24kHz到328.125MHz，满足不同应用场景的需求。请注意，虽然此文档提供了中文版信息，但为了获得最准确和最新的技术数据，建议在实际设计前查阅官方网站的英文版数据表（SNAS786）。此外，TI还提供技术文档、工具软件、支持社区等资源，帮助用户更全面地理解和应用CDCE6214-Q1。

CDCE6214-Q1

www.ti.com.cn

ZHCSK34A –AUGUST 2019–REVISED DECEMBER 2019

(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T

OUT-SKEW

. OUT2/OUT3 is matched within T

OUT-SKEW

7.17 LVCMOS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

O_LVCMOS

Output frequency 2 pF to GND, normal mode 0.024 200 MHz

OH_LVCMOS

Output high voltage

= 1 mA, VDDO_x is corresponding

supply voltage.

0.8 ×

VDDO_x

OL_LVCMOS

Output low voltage

= 1 mA, VDDO_x is corresponding

supply voltage.

0.2 ×

VDDO_x

Output high current Vout = 0.8 × VDDO_x, VDDO_x = 1.8 V -6 mA

Output high current Vout = 0.8 × VDDO_x, VDDO_x = 2.5 V -8.5 mA

Output high current Vout = 0.8 × VDDO_x, VDDO_x = 3.3 V -11.2 mA

Output low current Vout = 0.2 × VDDO_x, VDDO_x = 1.8 V 6 mA

Output low current Vout = 0.2 × VDDO_x, VDDO_x = 2.5 V 8.5 mA

Output low current Vout = 0.2 × VDDO_x, VDDO_x = 3.3 V 11.2 mA

RISE-FALL

Output rise/fall time 20/80%, C

= 5 pF, normal mode 300 500 700 ps

RISE-FALL

Output rise/fall time

20/80%, C

= 5 pF, slow mode, measured

on OUT0

1000 ps

SKEW

Output-to-output skew

(1)

LVCMOS-to-LVCMOS outputs, same

divide value

100 ps

SKEW

Output-to-output skew

(1)

LVCMOS-to-Differential outputs, same

divide value

400 ps

ODC Output duty cycle Not in PLL bypass mode 45 55 %

ON_LVCMOS

Output impedance Normal mode 45 60 75 Ω

ON_LVCMOS

Output impedance Slow mode 50 65 85 Ω

(1) Differential Output characteristic is trimmed in factory and trim settings are stored in EEPROM. Parameter not valid in Fall-back mode.

(2) PCIe test load slew rate

(3) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T

OUT-SKEW

. OUT2/OUT3 is matched within T

OUT-SKEW

. There is an additional skew 150 ps- 250 ps

between OUT1/OUT4 and OUT2/OUT3.

7.18 LP-HCSL Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

O_HCSL

Output frequency 0.024 350 MHz

Output high voltage

(1)

660 850 mV

Output low voltage -150 150 mV

DIFF

Differential Output Impedance

(1)

90 100 110 Ω

CROSS

Absolute crossing point

12-in, 100 Ω ±10% diff. trace with 2

pF±5%/pin in FR4.

250 550 mV

ΔV

CROSS

Relative crossing point variation with respect to average crossing point 140 mV

dV/dt Slew rate for rising and falling edge

differential, at V

CROSS

+/-150 mV,

O_HCSL

=100 MHz

(2)

1 4 V/ns

ΔdV/dt Slew rate matching

single-ended, at V

CROSS

+/-75 mV,

O_HCSL

=100 MHz

(2)

20 %

Vrb Output ringback voltage

Measured on differential output at 100

MHz and specifies minimum voltage from

zero crossing

-100 100 mV

Tstable Time elapsed until ringback Minimum time until ringback is allowed 500 ps

ODC Output duty cycle Not in PLL bypass mode 45 55 %

OUT-SKEW

Output skew

(3)

Same divide value, LP-HCSL to LP-HCSL 100 ps

CDCE6214-Q1

ZHCSK34A –AUGUST 2019–REVISED DECEMBER 2019

www.ti.com.cn

(1) Output Common Mode voltage and Differential output swing is dependent upon register settings DIFFBUF_IBIAS_TRIM,

LVDS_CMTRIM_DEC and LVDS_CMTRIM_INC. Parameters defined for DIFFBUF_IBIAS_TRIM=6h, LVDS_CMTRIM_DEC=0h and

LVDS_CMTRIM_INC=0h. Output Common Mode tested at DC.

(2) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T

OUT-SKEW

. OUT2/OUT3 is matched within T

OUT-SKEW

. There is an additional skew 150 ps- 250 ps

between OUT1/OUT4 and OUT2/OUT3.

7.19 LVDS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

O_PRG_AC

Output frequency 0.024 350 MHz

Output common mode

(1)

VDDO_X = 2.5 V, 3.3 V 1.025 1.2 1.375 V

Output common mode

(1)

VDDO_X = 1.8 V 0.85 0.95 1.05 V

Differential output voltage

(1)

VDDO_X = 1.8 V (F

out

< 200 MHz), 2.5 V,

3.3 V.

0.25 0.30 0.45 V

Differential output voltage

(1)

VDDO_X = 1.8 V & F

out

> 200 MHz 0.22 0.30 0.45 V

Output rise/fall times LVDS (20% to 80%) 450 650 900 ps

ODC Output duty cycle Not in PLL bypass mode 45 55 %

OUT-SKEW

Output skew

(2)

Same divide value, LVDS to LVDS output 100 ps

(1) Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.

7.20 Output Synchronization Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SU_SYNC

Setup time SYNC pulse

with respect to PLL reference rising edge

at 100 MHz with R=1

3 ns

H_SYNC

Hold time SYNC pulse

with respect to PLL reference rising edge

at 100 MHz with R=1

3 ns

PWH_SYNC

High pulse width for SYNC

With R = 1, at least 2 PFD periods + 24

feedback pre-scaler periods

60 ns

PWL_SYNC

Low pulse width for SYNC With R = 1, at least 1 PFD period 6 ns

Individual output enable time

(1)

tri-state to first valid rising edge 4 nCK

DIS

Individual output disable time

(1)

last valid falling edge to tri-state 4 nCK

(1) POR threshold voltage is the power supply voltage at which the internal reset is deasserted. It is qualified internally with PDN.

(2) VDD pin should monotonically reach 95% of its final value within supply ramp time. Parameters specified by characterization. All VDD

pins were tied together for this evaluation. For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin

until VDD pins have reached 95% of its final value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI

recommends to add a capacitor to GND on PDN pin to delay the release of reset.

7.21 Power-On Reset Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

THRESHOLD

POR threshold voltage

(1)

0.875 1.275 V

STARTUP

Start-up time

Start-up time after VDD reaches 95% to

the time outputs are toggling with correct

frequency (input = crystal or external

clock)

9 ms

VDD

Power supply ramp time

(2)

timing requirement for any VDD pin while

PDN=LOW

0.1 30 ms

7.22 I

C-Compatible Serial Interface Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input Voltage, Logic High

0.7 ×

VDD_REF

Input Voltage, Logic Low

0.3 ×

VDD_REF

Input Leakage Current VDD_REF ± 10% -5 5 µA

CDCE6214-Q1

www.ti.com.cn

ZHCSK34A –AUGUST 2019–REVISED DECEMBER 2019

C-Compatible Serial Interface Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low Level Output Voltage at 3 mA sink current 0.4 V

Input Capacitance 10 pF

OUT

Output Capacitance max bus capacitance per pin 400 pF

(1) t

H_SDA

is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V

IH(min)

of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

(3) The maximum t

H_SDA

could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of t

VD_SDA

a transition time. This maximum must only be met if the device does not stretch the LOW period (t

PWL_SCL

) of the SCL signal. If the

clock stretches the SCL, the data must be valid by the setup time before it releases the clock.

7.23 Timing Requirements, I

C-Compatible Serial Interface

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PW_G

Pulse Width of Suppressed Glitches 50 ns

SCL

SCL Clock Frequency Standard 100 kHz

SCL

SCL Clock Frequency Fast-mode 400 kHz

SU_STA

Setup Time Start Condition SCL=V

before SDA=V

0.6 µs

H_STA

Hold Time Start Condition

SCL=V

after SCL=V

After this time, the

first clock edge is generated.

0.6 µs

SU_SDA

Setup Time Data SDA valid after SCL=V

, f

SCL

=100 kHz 250 ns

SU_SDA

Setup Time Data SDA valid after SCL=V

, f

SCL

=400 kHz 100 ns

H_SDA

Hold Time Data

(1)

SDA valid before SCL=V

(2) (3)

µs

VD_SDA

Valid Data or Acknowledge Time f

SCL

=100 kHz

(3)

3.45 µs

VD_SDA

Valid Data or Acknowledge Time f

SCL

=400 kHz

(2)

0.9 µs

PWH_SCL

Pulse Width High, SCL f

SCL

=100 kHz 4.0 µs

PWH_SCL

Pulse Width High, SCL f

SCL

=400 kHz 0.6 µs

PWL_SCL

Pulse Width Low, SCL f

SCL

=100 kHz 4.7 µs

PWL_SCL

Pulse Width Low, SCL f

SCL

=400 kHz 1.3 µs

Input Rise Time 300 ns

Input Fall Time 300 ns

Output Fall Time 10 pF ≤ C

OUT

≤ 400 pF 250 ns

SU_STOP

Setup Time Stop Condition 0.6 µs

BUS

Bus-Free Time

Time between a Stop and a Start

condition

1.3 µs

7.24 Power Supply Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T

= -40°C to 105°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD_REF

VDD_REF supply current 25 MHz XTAL, DBL ON 8 mA

DD_VCO

VCO and PLL current

VCO

=2400 MHz, PSA = PSB = 4 and N-

divider = 48

14 mA

DD_OUT

Output Channel Current

IOD=6, LP-HCSL, 100MHz on OUT3 and

OUT4, 25MHz on OUT0

22 mA

DD_OUT

Output Channel Current

IOD = 6, LP-HCSL, 100 MHz on OUT1

and OUT2

17.5 mA

DD_PDN

Power down current using reset pin / bits 2.8 5 mA

DD_TYP

Typical current

4 x 100 MHz LVDS case using crystal

input and doubler, SSC off

50 70 mA

DD_TYP

Typical current

4 x 100 MHz LP-HCSL case using crystal

input and doubler, SSC off

65 90 mA

PSNR

Power supply noise rejection

OUTx = 100 MHz differential, on one of

VDDx injected sine wave at f

INJ

= 100 kHz

-61 dB

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