工业级单端口10/100Mb/s以太网物理层收发器TLK100

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"TI-TLK100.pdf 是一款由德州仪器(TI)推出的工业级单端口10/100Mb/s以太网物理层收发器，适用于各种严苛环境，如温度范围从-40°C到85°C。这款芯片提供多种保护功能，如±16kV的JEDEC HBM静电放电保护，以及低功耗设计，典型工作电流小于200毫安。它支持IEEE 802.3u标准的PCS（物理编码子层）和100BASE-TX传输接收器，具备电缆诊断功能，能实现IEEE 1588时间戳，确保在200米距离内无误差操作。此外，集成的物理子层带有自适应均衡和基线漂移补偿功能，兼容ANSI X3.263标准的TP-PMD。" 详细解释： 1. **Magnetics**：在以太网PHY收发器中，磁性元件通常指变压器，用于信号的耦合和隔离，确保数据在不同电压等级之间安全传输。 2. **MPU/CPU**：微处理器或中央处理器是系统的控制中心，负责处理指令和控制硬件操作。TI-TLK100通过Media Access Controller (MAC)接口与MPU/CPU通信，实现数据包的发送和接收。 3. **Media Access Controller (MAC)**：MAC子层是数据链路层的一部分，负责管理网络设备间的访问控制和帧传输。TLK100支持3.3V的MAC接口，并具备MII（Media Independent Interface）。 4. **MII**：MII是一种接口标准，允许PHY层和MAC层独立于物理媒介进行通信。它有并行接口，通常包含4对数据线，提供全双工的数据传输。 5. **10/100Mb/s**：表示该收发器支持10Mbps和100Mbps两种以太网速度，符合10BASE-T和100BASE-TX的标准。 6. **25-MHz Clock Source**：25MHz时钟源是TI-TLK100运行的基础，为数据传输提供定时。 7. **Status LEDs**：状态指示灯用于显示链接状态、速度、活动和碰撞检测等信息。 8. **RJ-45**：以太网连接的常见接口，用于连接网线。 9. **10BASE-T or 100BASE-TX**：10BASE-T是指10Mbps以太网，使用两对UTP线；100BASE-TX是指100Mbps快速以太网，使用两对非屏蔽双绞线。 10. **B0312-01 TLK100**：可能是该产品的特定型号或版本号。 11. **Auto-MDIX**：自动MDI/MDIX功能能够自动识别直通线缆（MDI）和交叉线缆（MDIX），简化网络布线。 12. **Programmable LEDs Support**：可编程LED支持，允许用户根据需要配置指示灯显示内容。 13. **Energy Detection Mode**：能量检测模式用于检测网络中的活动，有助于节能。 14. **10/100Mb/s Packet BIST (Built-in Self Test)**：内置的自我测试功能，可以检查10/100Mb/s数据包的传输功能。 15. **MIISerial Management Interface (MDC and MDIO)**：MII串行管理接口用于配置和监控PHY芯片，MDC是时钟信号，MDIO是数据接口。 16. **IEEE 802.3u MII**：这是快速以太网的标准，支持100BASE-TX。 17. **48-pin TQFP Package (7mm) × (7mm)**：48引脚薄型四方扁平封装，尺寸为7mm x 7mm，适用于紧凑型应用。 18. **IEEE 1149.1 JTAG**：联合测试行动组(JTAG)标准，用于测试和调试集成电路。 19. **Industrial Temp**：表明该器件适合在工业温度范围内工作。 20. **Applications**：TI-TLK100适用于各种应用场景，包括工业以太网、自动化系统、远程I/O模块、电力线通信等，尤其在需要高可靠性、低功耗和宽温工作的环境中表现出色。 TI-TLK100是一款高性能、工业级的以太网PHY收发器，提供全面的功能和保护，确保在各种环境下稳定可靠的数据通信。其设计考虑了效率、灵活性和易用性，是构建工业网络和自动化系统的理想选择。

MII_COL

MII_RXD_0

MII_RXD_1

MII_RXD_2

MII_RXD_3

2.2kW

VCC

PHYAD4=0 PHYAD3=0 PHYAD2=0 PHYAD1=1 PHYAD0=1

B0314-01

TLK100

www.ti.com

SLLS931B–AUGUST 2009–REVISED DECEMBER 2009

3.3 PHY Address

The 5 PHY address inputs pins are shared with the MII_RXD[3:0] pins and COL pin as shown in

Table 3-2.

Table 3-2. PHY Address Mapping

PIN # PHYAD FUNCTION RXD FUNCTION

24 PHYAD0 MII_COL

25 PHYAD1 MII_RXD_0

26 PHYAD2 MII_RXD_1

27 PHYAD3 MII_RXD_2

28 PHYAD4 MII_RXD_3

Each TLK100 or port sharing an MDIO bus in a system must have a unique physical address. With 5

address input pins, the TLK100 can support PHY Address values 0 (<00000>) through 31 (<11111>). The

address-pin states are latched into an internal register at device power-up and hardware reset. Because

all the PHYAD[4:0] pins have weak internal pull-down resistors, the default setting for the PHY address is

00000 (0x00h).

See Figure 3-1 for an example of a PHYAD connection to external components. In this example, the

PHYAD configuration results in address 00010 (0x02h).

Figure 3-1. PHYAD Configuration Example

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Product Folder Link(s): TLK100

LED_LINK

LED_SPEED

LED_ACT/COL

470 W 470 W470 W

2.2kW 2.2kW2.2kW

VCC

AN_EN=1 AN1=1 AN0=1

B0315-01

TLK100

SLLS931B–AUGUST 2009–REVISED DECEMBER 2009

www.ti.com

3.4 LED Interface

The TLK100 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED

configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes.

The LEDs can be controlled by configuration pin and/or internal register bits. Bits 6:5 of the LED Direct

Control register (LEDCR) selects the LED mode as described in Table 3-3.

Table 3-3. LED Mode Select

LED_CFG[1] LED_CFG[0]

Mode LED_LINK LED_SPEED LED_ACT

(bit 6) (bit 5) or (pin 22)

ON for Good Link ON in 100 Mb/s ON Pulse for Activity

1 don't care 1

OFF for No Link OFF in 10 Mb/s OFF for No Activity

ON for Good Link ON in 100 Mb/s None

2 0 0

BLINK for Activity OFF in 10 Mb/s

ON for Good Link ON in 100 Mb/s ON for Full Duplex

3 1 0

BLINK for Activity OFF in 10 Mb/s OFF for Half Duplex

The LED_LINK pin in Mode 1 indicates the link status of the port. It is OFF when no LINK is present. In

Mode 2 and Mode 3 it is ON to indicate Link is good and BLINK to indicate activity is present on either

transmit or receive channel. The blink rate is decided by the bits 9:8 of the LEDCR register (0x18). The

default blink rate is 5Hz.

The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. This LED is ON when the device is

operating in 100 Mb/s operation. The functionality of this LED is independent of mode selected.

The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED is ON

(Pulse) for Activity and OFF for No Activity. The width of the pulse is determined by the bits 14:13 of the

LEDCR register (0x18). The default pulse width is 200ms. In mode 3 this pin indicates the Duplex status

of operation. The LED is ON for Full Duplex and OFF for Half Duplex.

Bits 2:0 of the LEDCR register defines the polarity of the signals on the LED pins.

Since the Auto-Negotiation (AN) configuration options share the LED output pins, the external components

required for configuration-pin programming and those for LED usage must be considered in order to avoid

contention.

See Figure 3-2 for an example of AN connections to external components. In this example, the AN

programming results in Auto-Negotiation with 10/100 Half/Full-Duplex advertised.

Figure 3-2. AN Pin Configuration and LED Loading Example

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Product Folder Link(s): TLK100

MAC/

Switch

PCS

Signal

Process

PHY

AFE

PHY Digital

XFMR

RJ45

CAT5 Cable

LinkPartner

ReverseLoopback

TLK100

SLLS931B–AUGUST 2009–REVISED DECEMBER 2009

www.ti.com

3.5.2 Far-End Loopback

Far-end (Reverse) loopback is a special test mode to allow testing the PHY from link partner side. In this

mode data that is received from the link partner pass through the PHY's receiver, looped back on the MII

and transmitted back to the link partner. Figure 3-4 shows Far-end loopback functionality.

Figure 3-4. Block Diagram, Far-End Loopback Mode

The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII

While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface

and all data signals that come from the MAC are ignored.

3.6 BIST

The TLK100 incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit

testing or diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data

paths. The BIST testing can be performed using both internal loopback (digital or analog) or external loop

back using a cable fixture. The BIST simulates a real data transfer scenarios using real packets on the

lines. The BIST allows full control of the packets lengths and of the Inter Packet Gap (IPG)

The BIST is implemented with independent transmit and receive paths, with the transmit block generating

a continuous stream of a pseudo random sequence. The TLK100 generates a 23-bit pseudo random

sequence for doing the BIST test. The received data is compared to the generated pseudo-random data

by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of

error bytes that the PRBS checker received is stored in the BISECR register (0x72h).The number of

transmitted bytes that the PRBS checker received is stored in the BISBCR register (0x71h). The status of

whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS is in sync or

not and whether the packet generator is busy or not can be found by reading the BISSR register (0x17h).

The PRBS test can be put in a continuous mode or single mode by using the bit 15 of the BISCR register

(0x16h). In the continuous mode, when one of the PRBS counter reaches the maximum value the counter

starts counting from zero again. In the single mode when the PRBS counter reaches its maximum value

the PRBS checker stops counting.

TLK100 allows the user to control the length of the PRBS packet. By programming the BISPLR register

(0x7Bh) register one can set the length of the PRBS packet. There is also an option to generate a single

packet transmission of two types 64 and 1518 bytes through register bit – bit13 of the BISCR register

(0x16h). The single generated packet is composed of a constant data.

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Product Folder Link(s): TLK100

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