优化SSD写入性能：Prober利用顺序缓存策略

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本文探讨了"Prober：利用缓冲区中的顺序特性改善SSD的写入性能"这一研究主题，发表在2016年的《计算机科学前沿》(Frontiers in Computer Science)上，卷10，第5期，页码951-964。该研究的DOI是10.1007/s11704-016-5286-z。作者包括Wen ZHOU、Dan FENG、Yu HUA、Jingning LIU、Fangting HUANG、Yu CHEN以及Shuangwu ZHANG，他们来自武汉光电国家实验室和华中科技大学计算机科学与技术学院。固态硬盘(SSDs)因其高速读取性能和低功耗优势逐渐成为主流存储设备。为了提升写入性能并延长闪存寿命，SSD通常会利用内部动态随机访问内存(DRAM)作为缓存，将频繁重写的数据暂存起来，减少对闪存的编程操作次数。然而，现有的缓存管理算法主要依赖于数据访问模式来预测数据属性，这种策略在许多实际工作负载中并不完全适用。研究表明，在许多现实世界的场景下，大尺度的连续写入请求往往很少会在短时间内被重写。这意味着，当这些请求发生时，大量的热数据（即最近被频繁访问的数据）会被暂时缓存在DRAM中，这可能导致缓存效率不高，因为这些数据可能在未来很长一段时间内都不会再次写入。Prober算法正是针对这一问题提出的一种改进方案。 Prober通过深入挖掘缓存中的顺序特性，试图更智能地管理数据在缓存中的分布，避免无谓的缓存替换和程序操作。它可能采用一种预测机制，识别出那些虽然当前未被重写，但未来不太可能被重写的写入请求，从而优先将这些数据转移到闪存，释放出更多的缓存空间，进一步优化写入性能。此外，Prober也可能涉及到缓存策略的动态调整，根据工作负载的变化实时优化缓存使用，以提高整体系统效率。这项研究对于理解SSD缓存管理的关键因素，以及如何通过改进算法来适应不同类型的工作负载具有重要意义，可能对SSD设计者和优化工程师提供有价值的技术指导。通过实验证明，Prober能够有效提升SSD的写入性能，降低功耗，同时延长闪存使用寿命，从而推动固态存储技术的发展。

Wen ZHOU et al. Prober: exploiting sequential characteristics in buﬀer for improving SSDs write performance 953

In this paper, we make the following contributions.

First, in order to address the problem of cache pollution by

LWdata, we establish a block-level request sequence model,

called R-SEQ, and propose the Prober approach to identify

large sequential write request at early stage and label it as

cold page in buﬀer. Incorporated with existing buﬀer man-

agement scheme, SSD controller will migrate all the cold

pages to the tail of the queue and discard them from buﬀer

preferentially.

Second, in order to further lessen the response time, we

propose an actively write-back scheme. The proposed ap-

proach can write back LWdata in background and free up

space for incoming requests, which reduces average response

time dramatically.

Third, we implement Prober module and actively write-

back scheme on SSDsim. Extensive experiments under vari-

ous real-world workloads with diverse ratio of write requests

are conducted to examine write buﬀer hit ratio, average re-

sponse time and the number of erase operations. The experi-

mental results reﬂect that Prober is able to identify cold data

accurately and our schemes are very eﬀective.

The rest of this paper is organized as follows. Section 2

gives the background of SSDs and motivation of Prober. Sec-

tion 3 shows the details of Prober-based buﬀer management

and Section 4 shows the extensive evaluation of Prober. Sec-

tion 5 summarizes related work. Finally, in Section 6, we

conclude the paper.

2 Background and motivation

In this section, we present the background on SSDs to facil-

itate our discussion and analyze the important observations

that motivate our Prober design.

2.1 SSD overviews

Flash memory are widely used as solid-state drives (SSD) on

conventional machines. In the internal of SSD, FTL plays an

important role in managing DRAM buﬀer and ﬂash memory.

In general, FTL consists of address mapping, wear leveling,

garbage collection and buﬀer replacement components. Some

optional functions, such as data compression/encryption and

bad block management, are also applied in FTL. Among

them, address mapping scheme is the most important one and

the foundation of other algorithms.

According to mapping granularity, address mapping al-

gorithms are classiﬁed into page-level, block-level and hy-

brid mapping. For page-level mapping [3,4], a given logical

page number (LPN) can be mapped to arbitrary physical page

number (PPN) in the ﬂash memory. However, the table size

of page-level FTL is too large to be fully stored in the buﬀer,

which leads to severe performance degradation. To reduce

the space overhead of the address mapping table, block-level

FTL are proposed with a coarse-grained mapping pattern,

which records the mapping from logical block number (LBN)

to physical block number (PBN) by ensuring the oﬀset in the

physical block is the same as that in the logical block. Block-

level FTL shows lower space overhead than that of page-level

FTL. However, the update operations generated by rewritten

requests incur plenty of page migration and consume unaf-

fordable latency. To overcome their respective defects, sci-

entists propose a hybrid mapping scheme which divides the

entire blocks into data blocks and log blocks and adopts the

page-level and block-level mapping schemes in diﬀerent area.

Log blocks which store frequently updated pages use page-

level mapping, while data blocks store consecutive data and

adopt block-level mapping. Since log blocks are consumed

rapidly in random write applications, hybrid FTL consumes

longer time on transforming log blocks to data blocks, which

signiﬁcantly degrades the performance. All kinds of FTL al-

gorithms are well studied to overcome their ﬂaws and im-

prove storage performance.

In addition, another important component of FTL is the

buﬀer management module, which is widely studied in the

databases and operating systems. The size of each buﬀer en-

try can be a page or a block, which is decided by address map-

ping granularity. For page-level FTL, DRAM buﬀer manages

each page independently, thus it accommodates more hot

pages, achieving higher write performance with random ac-

cess pattern. While for the block-level FTL, pages with same

logical block address are gathered in buﬀer and written into

a physical block together when they are evicted from buﬀer.

It demonstrates higher write performance with sequential ac-

cess pattern. In this paper, we adopt page-level granularity

in DRAM buﬀer for our research. However, our scheme can

also be used in block-level FTL.

Given that asymmetry read/write latencies, the DRAM

buﬀer is mainly used to store dirty data generated by write

requests. Our scheme is based on pure write buﬀer, and it is

easy to be transplanted to hybrid buﬀer.

2.2 Research motivations for Prober

Operations associated with large ﬁles are ubiquitous in vari-

ous applications. On personal desktops and tablet computers,

there are frequent ﬁle copy operations such as downloading

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