PCI Express Base Specification Revision 3.0详解

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“PCIExpress®BaseSpecificationRevision3.0November10,2010” 《PCI Express® 基础规范第3.0版》是针对PCI Express（PCIe）架构的重要技术文档，旨在详细阐述PCI Express技术的核心要素、互连特性、结构管理和编程接口。该规范的目标是为系统及外设设计者提供指南，确保他们的产品能够符合PCI Express规范的要求。 PCIe是一种高速串行总线标准，用于连接计算机系统中的组件，如显卡、网卡、硬盘控制器等。PCIe技术通过点对点连接取代了传统的共享总线结构，提高了数据传输速度和系统性能。该规范的修订历史如下： 1.0版：初始发布，奠定了PCIe的基础。 1.0a版：包含了C1-C66和E1-E4.17的错误修正。 1.1版：整合了批准的错误修正和工程变更通知（ECNs）。 2.0版：增加了5.0 GT/s的数据速率，并整合了批准的错误修正和ECNs。 2.1版：包含2.0版的错误修正，并新增了多项ECNs，如内部错误报告、多播、原子操作、可调整大小的BAR能力、动态功率分配、基于ID的排序、延迟容忍报告、替代路由-ID解释（ARI）、扩展标签默认ECN、TLP处理提示、TLP前缀等。在PCI Express第3.0版中，速度进一步提升，数据传输速率达到了更高的水平，同时，规范还引入了新的功能和改进，以优化系统的可靠性和效率。例如，Resizable BAR能力允许动态调整设备的内存映射区域大小，动态功率分配则允许设备根据实际需求调整功耗。此外，错误报告和管理机制的增强确保了系统在出现异常情况时能够及时响应。 PCI Express 3.0规范的发布，标志着这一技术在带宽、效率和灵活性方面取得了显著进步，为高性能计算和数据中心应用提供了更强的支持。对于硬件开发者和系统集成商来说，理解和掌握这一规范至关重要，因为这将直接影响到他们设计的产品是否能够兼容最新的系统平台，并实现最优的性能表现。

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE......................................... 546

FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES................................................... 564

FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 568

IGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT.................................................. 569

IGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS...................................................... 571

FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY

MESSAGES ........................................................................................................................... 572

FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 576

IGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 576

IGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 577

FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER............................................................ 588

FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER................................................................ 595

FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER................................................................ 597

IGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER..................................................... 601

IGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 602

FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 603

FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE................................................................. 605

FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 605

FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 606

FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 608

FIGURE 7-14: DEVICE CONTROL REGISTER................................................................................. 613

FIGURE 7-15: DEVICE STATUS REGISTER.................................................................................... 620

FIGURE 7-16: LINK CAPABILITIES REGISTER............................................................................... 622

FIGURE 7-17: LINK CONTROL REGISTER..................................................................................... 627

FIGURE 7-18: LINK STATUS REGISTER........................................................................................ 635

FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 638

FIGURE 7-20: SLOT CONTROL REGISTER..................................................................................... 640

FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 644

FIGURE 7-22: ROOT CONTROL REGISTER.................................................................................... 646

FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 647

IGURE 7-24: ROOT STATUS REGISTER....................................................................................... 648

FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER........................................................................ 649

IGURE 7-26: DEVICE CONTROL 2 REGISTER.............................................................................. 654

IGURE 7-27: LINK CAPABILITIES 2 REGISTER............................................................................ 658

FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 660

FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 665

IGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT.................................. 668

FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 669

IGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE

............................................................................................................................................. 671

FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER........................ 672

IGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER........................................................ 673

FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER........................................................... 675

IGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER..................................................... 677

IGURE 7-37: CORRECTABLE ERROR STATUS REGISTER............................................................. 679

IGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 680

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 681

FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 683

FIGURE 7-41: ROOT ERROR COMMAND REGISTER...................................................................... 683

IGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 685

IGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 687

FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 688

FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 689

FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 690

IGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 691

IGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 692

FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 693

FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 694

FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER.................................................................. 695

IGURE 7-52: VC RESOURCE CONTROL REGISTER...................................................................... 697

IGURE 7-53: VC RESOURCE STATUS REGISTER......................................................................... 699

FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 701

FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES

............................................................................................................................................. 702

FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 703

FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER.................................. 704

FIGURE 7-58: SERIAL NUMBER REGISTER................................................................................... 705

FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 706

FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER............... 707

FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 708

FIGURE 7-62: LINK ENTRY.......................................................................................................... 709

FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 709

FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0.......................................................................... 711

FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1.......................................................................... 712

FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 713

FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER...................... 713

IGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 714

FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 717

IGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 719

IGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE................................. 720

FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER.......................................... 721

FIGURE 7-73: POWER BUDGETING DATA REGISTER.................................................................... 722

IGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 724

FIGURE 7-75: ACS EXTENDED CAPABILITY................................................................................ 725

IGURE 7-76: ACS EXTENDED CAPABILITY HEADER ................................................................. 725

FIGURE 7-77: ACS CAPABILITY REGISTER ................................................................................. 726

FIGURE 7-78: ACS CONTROL REGISTER ..................................................................................... 727

IGURE 7-79: EGRESS CONTROL VECTOR REGISTER................................................................... 730

FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 731

IGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED

CAPABILITY HEADER........................................................................................................... 731

IGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 733

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER.............................................................. 733

FIGURE 7-84: PORT VC CAPABILITY REGISTER 1 ....................................................................... 734

FIGURE 7-85: PORT VC CAPABILITY REGISTER 2 ....................................................................... 736

IGURE 7-86: PORT VC CONTROL REGISTER .............................................................................. 737

IGURE 7-87: PORT VC STATUS REGISTER ................................................................................. 738

FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER.................................................................. 738

FIGURE 7-89: VC RESOURCE CONTROL REGISTER...................................................................... 740

FIGURE 7-90: VC RESOURCE STATUS REGISTER......................................................................... 742

IGURE 7-91: PCI EXPRESS VSEC STRUCTURE.......................................................................... 746

IGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 746

FIGURE 7-93: VENDOR-SPECIFIC HEADER .................................................................................. 747

FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 748

FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 748

IGURE 7-96: VENDOR ID AND DEVICE ID ................................................................................. 749

IGURE 7-97: RCRB CAPABILITIES ............................................................................................ 750

FIGURE 7-98: RCRB CONTROL................................................................................................... 750

FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE................................................. 751

FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER .................................................... 751

FIGURE 7-101: MULTICAST CAPABILITY REGISTER .................................................................... 752

FIGURE 7-102: MULTICAST CONTROL REGISTER ........................................................................ 753

FIGURE 7-103: MC_BASE_ADDRESS REGISTER ......................................................................... 754

FIGURE 7-104: MC_RECEIVE REGISTER ..................................................................................... 754

FIGURE 7-105: MC_BLOCK_ALL REGISTER............................................................................... 755

FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER............................................................ 756

FIGURE 7-107: MC_OVERLAY_BAR.......................................................................................... 757

FIGURE 7-108: RESIZABLE BAR CAPABILITY............................................................................. 759

FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 759

FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER............................................................. 760

FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER ................................................................ 761

FIGURE 7-112: ARI CAPABILITY................................................................................................. 762

IGURE 7-113: ARI CAPABILITY HEADER .................................................................................. 763

FIGURE 7-114: ARI CAPABILITY REGISTER ................................................................................ 763

IGURE 7-115: ARI CONTROL REGISTER .................................................................................... 764

IGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 765

FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER ............................................................... 765

FIGURE 7-118: DPA CAPABILITY REGISTER ............................................................................... 766

IGURE 7-119: DPA LATENCY INDICATOR REGISTER................................................................. 767

FIGURE 7-120: DPA STATUS REGISTER ...................................................................................... 767

IGURE 7-121: DPA CONTROL REGISTER ................................................................................... 768

FIGURE 7-122: DPA POWER ALLOCATION ARRAY ..................................................................... 768

FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 769

IGURE 7-124: LTR EXTENDED CAPABILITY HEADER................................................................ 769

FIGURE 7-125: MAX SNOOP LATENCY REGISTER ....................................................................... 770

IGURE 7-126: MAX NO-SNOOP LATENCY REGISTER................................................................. 770

IGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE .......................................................... 771

IGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER............................................ 772

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER............................................................ 772

FIGURE 7-130: TPH REQUESTER CONTROL REGISTER................................................................ 774

FIGURE 7-131: TPH ST TABLE ................................................................................................... 775

IGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE........................ 776

IGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER.............................. 776

FIGURE 7-134: LINK CONTROL 3 REGISTER ................................................................................ 777

FIGURE 7-135: LANE ERROR STATUS REGISTER ......................................................................... 778

FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER ......................................................... 778

IGURE 7-137: LANE ((MAXIMUM LINK WIDTH – 1):0) EQUALIZATION CONTROL REGISTER .... 779

IGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER

COMMUNICATION MODELS.................................................................................................. 784

FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND

CONGESTION........................................................................................................................ 785

IGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS

............................................................................................................................................. 790

FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF 0 ............................... 810

FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 819

FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK................................ 827

FIGURE G-2: PMUX LINK .......................................................................................................... 828

FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS ...................................................... 829

FIGURE G-4: PMUX PACKET...................................................................................................... 836

FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING)....................................... 837

FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING)................................ 839

FIGURE G-7: PMUX EXTENDED CAPABILITY ............................................................................. 843

FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER............................................................... 843

FIGURE G-9: PMUX CAPABILITY REGISTER............................................................................... 844

FIGURE G-10: PMUX CONTROL REGISTER................................................................................. 846

FIGURE G-11: PMUX STATUS REGISTER.................................................................................... 847

FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY....................................................................... 850

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

Tables

TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 54

ABLE 2-2: FMT[2:0] FIELD VALUES ............................................................................................ 59

TABLE 2-3: FMT[2:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 60

ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 61

ABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 66

TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 66

TABLE 2-7: HEADER FIELD LOCATIONS FOR NON-ARI ID ROUTING............................................. 68

TABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING..................................................... 68

ABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 70

ABLE 2-10: ORDERING ATTRIBUTES ........................................................................................... 75

TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 76

TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS...................................................................... 76

TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS................................................. 77

TABLE 2-14: TPH TLP PREFIX BIT MAPPING ............................................................................... 81

TABLE 2-15: LOCATION OF PH[1:0] IN TLP HEADER.................................................................... 82

TABLE 2-16: PROCESSING HINT ENCODING .................................................................................. 82

TABLE 2-17: LOCATION OF ST[7:0] IN TLP HEADERS .................................................................. 83

TABLE 2-18: MESSAGE ROUTING.................................................................................................. 85

TABLE 2-19: INTX MECHANISM MESSAGES ................................................................................. 86

TABLE 2-20: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 88

TABLE 2-21: POWER MANAGEMENT MESSAGES........................................................................... 90

TABLE 2-22: ERROR SIGNALING MESSAGES ................................................................................. 91

TABLE 2-23: UNLOCK MESSAGE................................................................................................... 92

TABLE 2-24: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 92

TABLE 2-25: VENDOR_DEFINED MESSAGES................................................................................. 93

TABLE 2-26: IGNORED MESSAGES ................................................................................................ 95

TABLE 2-27: LTR MESSAGE ......................................................................................................... 95

TABLE 2-28: OBFF MESSAGE....................................................................................................... 96

ABLE 2-29: COMPLETION STATUS FIELD VALUES....................................................................... 98

TABLE 2-30: LOCAL TLP PREFIX TYPES..................................................................................... 101

ABLE 2-31: END-END TLP PREFIX TYPES................................................................................. 102

ABLE 2-32: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES.......................... 117

TABLE 2-33: CALCULATING LOWER ADDRESS FROM 1

DW BE............................................... 118

TABLE 2-34: ORDERING RULES SUMMARY ................................................................................. 123

ABLE 2-35: TC TO VC MAPPING EXAMPLE .............................................................................. 131

TABLE 2-36: FLOW CONTROL CREDIT TYPES ............................................................................. 135

TABLE 2-37: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 135

ABLE 2-38: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 136

TABLE 2-39: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144

TABLE 2-40: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144

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