Pic16(l)f1508/9微控制器开发与编程指南

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"pic16(l)f1508/9 - 重要的开发文档，涵盖了Microchip Technology Inc.的微控制器的使用、开发、仿真、调试和编程方法。" 本文档详细介绍了Pic16(L)F1508/9系列微控制器的特性与功能，这些器件是高性能的RISC（精简指令集计算机）CPU，适用于各种嵌入式系统应用。以下是对这些微控制器关键特性的深入解释： 1. **C编译器优化架构**：设计时考虑了C语言编译器的效率，使得代码更紧凑，运行更高效。 2. **指令集**：仅包含49条指令，简化了编程，同时保证了高效的执行速度。 3. **操作速度**：支持从直流到20MHz的时钟输入，每条指令周期仅为200ns，提供快速响应能力。 4. **中断功能**：具备中断能力，并自动保存上下文，便于在处理中断事件时保持程序状态。 5. **硬件堆栈**：16级深的硬件堆栈，可选的溢出/下溢复位，确保程序流程控制的稳定性。 6. **寻址模式**：包括直接、间接和相对地址模式，其中两个完整的16位文件选择寄存器（FSRs）允许读取程序和数据存储器。 7. **灵活的振荡器结构**：内置16MHz振荡器，出厂校准精度为±1%，软件可选频率范围从16MHz到31kHz。此外，还包括31kHz低功耗内部振荡器和高达20MHz的三种外部时钟模式。 8. **特殊微控制器特性**： - **工作电压范围**：Pic16LF1508/9支持1.8V至3.6V，而Pic16F1508/9支持2.3V至5.5V。 - **自编程功能**：可以在软件控制下进行自我编程，方便更新固件。 - **上电复位(POR)**：确保设备在上电后处于已知状态。 - **上电定时器(PWRT)**：在电源稳定之前提供延迟，防止误操作。 - **可编程低功耗brown-out重置(LPBOR)**：检测电源电压下降并执行安全重置。 - **扩展看门狗定时器(WDT)**：可编程周期从1毫秒到256秒，防止程序卡死。 - **程序保护**：提供可编程的代码保护机制，增强固件安全性。 - **串行在线编程**：In-Circuit Serial Programming™技术允许在电路板上对器件进行编程和调试，无需额外的硬件。这些特性使得Pic16(L)F1508/9成为开发嵌入式系统、物联网设备、传感器节点等应用的理想选择。对于开发者而言，理解这些特性并熟练运用，将有助于提升项目效率和产品质量。

 2011-2015 Microchip Technology Inc. DS40001609E-page 17

PIC16(L)F1508/9

3.2.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.2.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

3.2.1.2 Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIW instruction will place the

lower eight bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The HIGH operator will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

constants

DW DATA0 ;First constant

DW DATA1 ;Second constant

DW DATA2

DW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

ADDLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants;MSb sets

automatically

MOVWF FSR1H

BTFSC STATUS, C ;carry from ADDLW?

INCF FSR1h, f ;yes

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

 2011-2015 Microchip Technology Inc. DS40001609E-page 19

PIC16(L)F1508/9

3.3.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO

and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section

28.0 “Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —

PD ZDC

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO

: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD

: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow

bit

(1)

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2011-2015 Microchip Technology Inc. Status DS40001609E-page 21

PIC16(L)F1508/9

3.3.5 DEVICE MEMORY MAPS

The memory maps for Bank 0 through Bank 31 are shown in the tables in this section.

TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 0-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Tabl e 3 - 2)

080h

Core Registers

(Tabl e 3 - 2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch

— 30Ch — 38Ch —

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh

— 30Dh — 38Dh —

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh

—28Eh—30Eh—38Eh—

00Fh

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h

—090h—110h—190h—210h—290h

—

310h

— 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h

SSP1BUF

291h

—

311h

—

391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h

SSP1ADD

292h

—

312h

—

392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h

SSP1MSK

293h

—

313h

—

393h

IOCAF

014h

—094h— 114h CM2CON1 194h PMDATH 214h

SSP1STAT

294h

—

314h

—

394h IOCBP

015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h

SSP1CON1

295h

—

315h

—

395h IOCBN

016h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h

SSP1CON2

296h

— 316h — 396h IOCBF

017h

TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h

SSP1CON3

297h

— 317h — 397h —

018h

T1CON 098h

—118h

DAC1CON0

198h —218h

—

298h

— 318h — 398h —

019h

T1GCON 099h OSCCON 119h

DAC1CON1

199h

RCREG

219h

—299h— 319h — 399h —

01Ah

TMR2 09Ah OSCSTAT 11Ah

—19Ah

TXREG

21Ah —29Ah—31Ah—39Ah—

01Bh

PR2 09BhADRESL11Bh

—19Bh

SPBRG

21Bh —29Bh—31Bh

—

39Bh

—

01Ch

T2CON 09Ch ADRESH 11Ch

— 19Ch

SPBRGH

21Ch — 29Ch — 31Ch

—

39Ch

—

01Dh

— 09Dh ADCON0 11Dh APFCON 19Dh

RCSTA

21Dh

—

29Dh

—

31Dh

—

39Dh

—

01Eh

—

09Eh ADCON1 11Eh

—

19Eh

TXSTA

21Eh

—

29Eh

—

31Eh

—

39Eh

—

01Fh

—

09Fh ADCON2 11Fh

—19Fh

BAUDCON

21Fh

—

29Fh

—

31Fh

—

39Fh

—

020h

General

Purpose

80 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

Unimplemented

Read as ‘0’

220h

Unimplemented

Read as ‘0’

2A0h

Unimplemented

Read as ‘0’

320h

Unimplemented

Read as ‘0’

3A0h

Unimplemented

Read as ‘0’

0EFh

06Fh

16Fh 1EFh 26Fh 2EFh

36Fh 3EFh

070h

Common RAM

0F0h

Common RAM

(Accesses

70h – 7Fh)

170h

Common RAM

(Accesses

70h – 7Fh)

1F0h

Common RAM

(Accesses

70h – 7Fh)

270h

Common RAM

(Accesses

70h – 7Fh)

2F0h

Common RAM

(Accesses

70h – 7Fh)

370h

Common RAM

(Accesses

70h – 7Fh)

3F0h

Common RAM

(Accesses

70h – 7Fh)

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

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