窄窗LDMOS SCR：设计优化与性能提升分析

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“窄窗LDMOS SCR（雪崩倍增二极管雪崩二极管保护器件）的设计与分析” 本文主要探讨了一种改进的LDMOS SCR（半导体可控硅），被称为非LDMOS SCR，它是在0.5微米5V/18V/24V CDMOS工艺中实现的。这种新型保护器件旨在提高静电放电（ESD）防护性能，同时优化其关键参数，如二次击穿电流（It2）和触发电压（Vh）。 LDMOS（横向扩散金属氧化物半导体）结构常用于高压功率应用，而SCR（半导体可控硅）则是一种能自我维持导通状态的器件，常用于ESD保护电路。在非LDMOS SCR设计中，通过去除特定的LDMOS结构，可以达到提高器件性能的目的。理论分析和传输线脉冲（TLP）测试系统被用来预测和表征所提出的ESD保护器件的性能。TLP测试是一种广泛用于评估半导体器件浪涌耐受能力的方法，它可以提供精确的电流-电压特性数据。根据测量结果，非LDMOS SCR相较于传统的LDMOS SCR，显著提升了二次击穿电流，从3.87A增加到4.64A，这意味着它能承受更大的瞬态电流而不损坏。同时，非LDMOS SCR降低了触发电压，从33V减小到21.4V，这使得器件能更快地响应ESD事件，提高了ESD保护的效率。此外，文章还讨论了D2和D3（如图1(c)所示）尺寸对保持电压的影响。D2和D3是SCR中的关键组件，它们的尺寸调整直接影响到器件在导通状态下的电压稳定性。通过增加D2的宽度，保持电压从11.7V提升到14.7V，表明这种设计可以更好地控制和稳定保护电路在ESD事件后的状态。这篇研究论文提供了关于窄窗LDMOS SCR设计的新见解，展示了如何通过优化结构和尺寸来改善ESD保护器件的关键性能参数，这对于高电压功率器件的ESD防护策略具有重要的实践意义。这项工作对于提升半导体设备的可靠性，尤其是在恶劣环境下的运行，有着重要的理论和技术支持。

Design and analysis of LDMOS_SCR with narrow

windows

Xiang-Liang Jin

1, 2*

, Yi-Fei Zheng

1,2

, Yang Wang

1,2

, Zi-Jie Zhou

1,2

Faculty of Physics and Optoelectronic Engineering, Xiangtan University, Xiangtan 411105, China 1

Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on a Chip, Xiangtan 411105 2.

Phone: +86 0731 58292195

E-mail –jinxl@xtu.edu.cn

Abstract- In this paper, an improved LDPMOS_SCR without a

LDPMOS structure (NonLDPMOS_SCR) is discussed, which is

realized in 0.5-µm 5V/18V/24V CDMOS process. The theoretical

analysis and transmission line pulse (TLP) testing system are used

to predict and characterize the proposed ESD protection devices.

According to the measurement results, compared with the normal

LDPMOS_SCR, NonLDPMOS_SCR elevates the second

breakdown current (It2) from 3.87A to 4.64A and decreases the

trigger voltage (Vh) from 33V to 21.4V without expanding device

area. Furthermore, the influence of the size of D2 and D3 (as

shown in Fig.1(c)) on holding voltage is discussed. The TLP results

conﬁrm that by adding the width of D2, the holding voltage is

increased from 11.7V to 14.79V. And by adding the width of D3,

the holding voltage is increased from 11.7V to 15.9V. It is proved

that increasing the width of D3 in the proposed device is more

effective in increasing the holding voltage.

I. INTRODUCTION

With the rapid development of power integrated

technology, high-voltage (HV) devices are widely used in

smart-power integrated circuits, such as automotive electronics,

high-voltage circuit drivers, and power management circuits

[1-2]. And electrostatic discharge (ESD) reliability has become

one of the most severe reliability issues in HV devices. ESD

protection devices for HV ICs require a reasonable

, a high

holding voltage (

hold

) and strong ESD robustness within a

small device area [3]. Laterally-diffused

metal-oxide-semiconductor (LDMOS) with embedded silicon

control rectiﬁer (LDMOS-SCR) is proposed for providing ESD

protection in HV process due to its good compatibility with

CMOS processes [4-5]. However, with the feature size of HV

ICs scaling down, LDMOS-SCR served as ESD protection is

greatly limited by its weak latch-up immunity and the high

trigger voltage(

) . Generally, the latch-up immunity is

determined by the

hold

and the holding current (

). Some

prior studies have been proposed to increase

hold

[6-8].

However, the consumed silicon area and the latch-up risk of

LDMOS-SCR could not be sufﬁciently minimized by these

methods. In this work, high performance in s mall

areas(47um*56um) of NonLDPMOS_SCR has been achieved

though the increase in the width of D2 and D3. And the result of

TLP has some guidance as to the trade-off between the holding

voltage and the maximum degree of protection required for the

device.

II. Devices Structure and ESD Characteristic Analysis

The LDPMOS_SCR device illustrated in Fig.1 (a) is a

PNPNP DDSCR consisting of two LDPMOS devices with their

drain in common. The P+ region in PW is reserved for the

purpose of obeying to the design rule without any modifications

to the structure. The drain electrode is floating. The bulk, source,

and gate electrode of each LDPMOS are combined to form

anode or cathode of the device. When a positive ESD pulse is

stressed on the anode of LDPMOS_SCR, the gate, source, and

bulk of LDPMOS device Mp1 are all connected to high

potential. Mp1 is shutting off. The other LDPMOS device Mp2

is on-state because the gate of Mp2 is bound to ground. The b-c

(PW/NWD) junction of the parasitic BJT (T1//T3) in Mp1 is

reverse biased, and it generates a large amount of electron-hole

pairs when the voltage reaches a level of avalanche breakdown.

Only if the voltage on the parasitic resistor R1 is large enough to

forward bias the e-b (P+/NWD) junction of T1//T3, the current

conducting by T1//T3 will drive the parasitic SCR composed of

T1//T3 and T2, and the SCR path will become the major

discharging path eventually. Hence, the lateral PNP BJT T1//T3

and NPN BJT T2 pair form a regenerative thyristor to conduct

the ESD current through the real line path shown in Fig.1 (b).

When a negative ESD pulse is applied to the anode of this

device, it is equivalent as a positive ESD pulse is stressed on the

cathode. Since the device structure is symmetric, its working

mechanism will be similar to the case that when a positive ESD

pulse is applied to the anode. But device triggering will occur at

the NWD/PW junction on the cathode side.

Fig.1(c) shows the NonLDPMOS_SCR. Compared with

LDPMOS_SCR, the NWD-PW junction is moved under the P+

diffusion region of the drain. So there is no LDPMOS structure

in NonLDPMOS_SCR. Fig.2 (d) is the equivalent schematic

when a positive ESD pulse is stressed on the anode. Its operation

mechanism is almost the same as LDPMOS_SCR. The only

difference is that when a positive ESD pulse is stressed on the

anode of NonLDPMOS_SCR, the Mp1 and Mp2 are neither

on-state nor off-state. Because there is no channel in Mp1 and

Mp2, which can be considered respectively as resistor Rmp1

and Rmp2, as shown in Fig.2(d).

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