Chrontel CH7025/CH7026高清编码器：功能概览与特性

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CH7025/CH7026是一款由Chrontel公司开发的专为消费电子产品设计的STV（Single-Transistor Video）/VGA编码器。该芯片的主要特点是针对便携式设备和其他适配的显示设备，提供高质量的视频信号输出。它支持多种输出格式，包括电视标准（如NTSC和PAL）、模拟RGB输出用于VGA同步信号，以及可编程复合同步信号生成，能够满足不同的显示需求。该芯片的核心特性包括三个内置的10位高速数字-模拟转换器（DAC），这使得CH7025/CH7026能够在单路、双路或三路输出模式下灵活地提供CVBS（Composite Video Broadcast Signal）、YPbPr（逐行扫描色彩子采样）以及RGB信号。此外，它还配备了一块16Mbit的静态随机存取存储器（SRAM）作为帧缓冲器，支持帧率转换，有助于优化视频处理性能和稳定性。内置的灵活缩放引擎确保了无闪烁的图像显示，这对于高分辨率视频的处理尤为重要。该编码器提供了多种输入接口选择，包括24位/18位/16位/15位/12位/8位的数字输入，支持各种RGB（如RGB888、RGB666、RGB565等）格式、YCbCr（4:4:4 YCbCr和ITU 656）以及2或3路多路复用输入，兼容CPU接口，适应不同的图像源和处理需求。在分辨率方面，CH7025/CH7026支持高达800x800像素和1024x650像素（包括常见的220x176、320x240、640x480和7英寸等）的输入，这使得它适用于广泛的应用场景，如便携式电视、游戏设备、嵌入式系统等，确保了清晰且高效的视频编码和传输。 CH7025/CH7026以其高度灵活性、多格式支持和出色的图像处理能力，为消费电子产品的视频输出提供了强大的解决方案，是设计者在开发需要高质量视频输出功能的产品时的理想选择。

CHRONTEL CH7025/CH7026

Preliminary

10 201-0000-089 Rev. 0.63, 9/27/2007

Pin # Type Symbol Description

36 Out XO Crystal Output

For master mode and some situation of the slave mode, a parallel

resonance crystal (± 20 ppm) should be attached between this pin and

XI / FIN. However, if an external CMOS clock is attached to XI/FIN,

XO should be left open.

50 In GCLK External Clock Inputs

The input is the clock signal input to the device for use with the H, V,

DE and D[23:0] data.

2 Out VSO/CSYNC Vertical sync signal output or composite sync output,

The amplitude of this pin is from 0 to AVDD

1 Out HSO/CSYNC Horizontal sync signal output or composite sync output,

The amplitude of this pin is from 0 to AVDD

3 Out CSYNC Composite sync output,

The amplitude of this pin is from 0 to AVDD

51 Power VDDIO IO supply voltage (1.2-3.3V)

69 Power DVDD Digital supply voltage (1.8V)

8,12,37,49 Power AVDD Analog supply voltage

33 Power AVDD_PLL PLL supply voltage

24,28 Power AVDD_DAC DAC power supply

10,18 Power VDDQ_MEM SDRAM output buffer supply voltage

14,44,45 Power VDD_MEM SDRAM device supply voltage

68 Power DGND Digital supply ground

7,11,34,48 Power AGND Analog supply ground

32 Power AGND_PLL PLL supply ground

26,30 Power AGND_DAC DAC supply ground

9,19 Power GNDQ_MEM SDRAM output buffer supply ground

13,46,47 Power GND_MEM SDRAM device supply ground

CHRONTEL CH7025/CH7026

Preliminary

201-0000-089 Rev. 0.63, 9/27/2007 11

2.0 Functional Description

2.1 Modes of operation

The CH7025/CH7026 is capable of being operated as a TV encoder. Table 3 describes the possible operating modes.

An ‘i’ following a number in the Input Scan Type column indicates an interlaced input where the number indicates the

active number of lines per frame. Basically, CH7025/CH7026 can take non-interlaced data from graphics controller and

encode it to analog NTSC and PAL waveforms. It can also take in interlaced data from sources like MPEG decoder and

perform simple SDTV encoding.

Table 3: Operation modes

Input Scan Type Input Data

Format

Output scan

Type

Output

Format

Operating Mode Described

In section

Non-Interlaced

RGB /

YCrCb

Interlaced CVBS,

S-Video

SDTV encoder (NTSC / PAL) with

non-interlaced input

2.1.1

Interlaced

(480i, 576i)

RGB /

YCrCb

Interlaced CVBS,

S-Video

SDTV encoder (NTSC / PAL) with

interlaced input

2.1.2

YCrCb signal has the following characteristics (assumed to be gamma corrected):

Y = 77/256 * R + 150/256 * G + 29/256 * B

Cr = 131/256 * R – 110/256 * G – 21/256 * B + 128

Cb = - 44/256 * R – 87/256 * G + 131/256 * B + 128

Data is 8-bit or 10-bit width and follows ITU-R BT.656 format.

Data sequence is like : Cb

3, ……

Where Cb

are co-sited samples, and Y

is the following Luma sample.

CH7025/CH7026 can also support analog RGB output through on DACs. Either horizontal and vertical sync or

composite sync can be provided (DE signal can also be provided optionally). This kind of output format can be

accepted by CRT or LCD monitors.

2.1.1 Graphics Controller to SDTV Encoder

CH7025/CH7026 is mainly designed as an SDTV encoder targeting handheld device market or some other applications

that require TV out function such as displays in automobile. In this mode, the graphics controller of the handheld

system or other system will send out non-interlaced data, sync and clock signals to CH7025/CH7026. CH7025/CH7026

can run in clock slave mode. In clock slave mode, no reference clock is output to the graphics controller. So the crystal

becomes optional in the slave mode. However, if the clock from the graphics controller cannot meet the accuracy

requirement of color sub-carrier generation, the crystal is still required, and it will be discussed in the later part of this

document. Not only horizontal and vertical sync signals are normally sent to the device from the graphics controller,

but also they can be embedded into the data stream in YCbCr input data formats. CH7025/CH7026 can also internally

generate H and V sync then send them to graphics controller as reference. Input data can be unitary, 2X or 3X

multiplexed , and the G_CLK clock signal can be 1X, 2X or 3X times the pixel rate. Input data will be scaled, scan

converted and filtered, then encoded into the selected video standard and output from the video DACs. Various NTSC

and PAL formats are supported. The device can output data in S-Video and CVBS format. The graphics resolutions

supported are from 176x144 to 800x600. The typical resolutions are shown in Table 4. The device is capable of adding

Macrovision encoding to the output signal (CH7025 only).

Table 4: Typical input resolution

Typical

input

resolution

176

144

176

220

176

240

320

240

480

640

480

720

480

720

576

800

480

800

576

856

480

800

600

Output

format

NTSC_M, NTSC_J, NTSC_443

PAL_B/D/G/H/I, PAL_M, PAL_N, PAL_Nc, PAL_60

CHRONTEL CH7025/CH7026

Preliminary

12 201-0000-089 Rev. 0.63, 9/27/2007

2.1.2 ITU-R BT.601/656 TV Encoder

In interlaced data, sync and clock signals are input to the CH7025/CH7026 from a graphics controller or an MPEG

decoder device. The YCbCr data format is most commonly used in these modes, but RGB data can be used as well. Not

only horizontal and vertical sync signals are normally sent to the CH7025/CH7026 from the graphics device, but also

they can be embedded into the data stream in YCbCr input data formats. In some cases, the chip itself can self generate

H and V sync as reference for graphics controller. Data can be unitary, 2X or 3X multiplexed, and the GCLK clock

signal can be 1X , 2X or 3X times the pixel rate. Input data bypasses the scaling, scan conversion and filtering blocks,

is encoded into the selected video standard and output from the video DACs. NTSC and PAL formats are supported.

The device can output data in S-Video and CVBS format. The graphics resolutions supported for ITU-R BT.601/656

TV output are shown in Table 5. The device is capable of adding Macrovision to the output signal (CH7025 only). The

timing of the sync signals is shown in Figure 4 below. Note that the alignment of the VSYNC signal to the HSYNC

signal changes from field 1 to field 2 to allow the CH7025/CH7026 to identify the correct field.

Table 5: ITU-R BT.601/656 TV Encoder Operating Modes

Input Resolution TV Output Standard

720x480i NTSC

720x576i PAL

H In/Out

V Out

(Odd Field

Master Mode)

V Out

(Even Field

Master Mode)

V In

(Odd Field

Slave Mode)

V In

(Even Field

Slave Mode)

Figure 4: Interlaced Sync Input/Output Timing

Table 6: Interlaced Sync Input/Output Timing

Symbol Parameter Min Typ Max Unit

Total Line Period

SDTV

63.5 / 64.0

Hsync Width

When output from CH7025/CH7026

When input to CH7025/CH7026

Pixel clocks

Odd Field (Field 1) V SYNC out to H SYNC out

alignment

0 us

Even Field (Field 2) V SYNC out delay from H SYNC

out

0.5*T

Odd Field (Field 1) V SYNC in to H SYNC in alignment 0 W

- T

PCK

Even Field (Field 2) V SYNC in delay from H SYNC in W

- T

PCK

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