QCA9882 Wi-Fi手册： Qualcomm Atheros 秘密技术数据

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"QCA9882 Wifi手册" QCA9882是高通(Atheros)公司的一款高性能Wi-Fi芯片，主要用于无线网络连接。该手册详细介绍了QCA9882芯片的功能、规格和使用方法，是针对硬件开发者、网络工程师以及相关专业人士的重要参考资料。 1. **芯片概述**： QCA9882是一款双频段无线网络适配器，支持802.11ac Wi-Fi标准，能够提供高速无线连接，最大理论速度可达1300Mbps。这款芯片集成了2.4GHz和5GHz频段，旨在提供稳定且高效的无线网络服务。 2. **技术特性**： - **802.11ac标准**：支持第五代Wi-Fi技术，提供比802.11n更快的数据传输速度。 - **MIMO技术**：多输入多输出技术，通过多个天线同时传输和接收数据，提高网络性能。 - **beamforming**：波束成形技术，优化无线信号传播，增强信号强度和覆盖范围。 - **高级调制编码方案**：如256-QAM，提高信道效率，提升数据传输速率。 - **功耗管理**：设计有节能特性，适用于移动设备和物联网(IoT)应用。 3. **配置与设置**：手册将详细解释如何配置QCA9882芯片，包括设置无线网络参数、配置安全选项（如WPA/WPA2）、网络模式（如AP、客户端、桥接等）以及射频(RF)参数调整。 4. **硬件接口**： QCA9882可能包含多种接口，如PCIe、USB或SDIO，用于连接主机系统。手册会涵盖这些接口的连接方式和相关硬件兼容性问题。 5. **软件支持**：可能包括驱动程序安装、固件升级和API接口指南，以便开发者集成到他们的系统或应用中。 6. **故障排查与诊断**：提供了常见的问题解决方案和故障排除步骤，帮助用户解决在使用QCA9882过程中遇到的问题。 7. **合规性与安全**：由于涉及到无线通信，手册还会涵盖国际和美国的无线电频谱法规，以及安全认证（如FCC、CE等）的相关信息。 8. **知识产权声明**：高通(Atheros)对QCA9882的技术资料拥有严格的版权和保密规定，禁止未经授权的公开分发、复制或修改。使用者必须遵守这些条款，以避免法律纠纷。 QCA9882手册是深入理解并有效利用这款Wi-Fi芯片的关键资源，它涵盖了从硬件安装到软件配置的所有环节，是实现高性能无线网络连接的基础。对于那些需要开发基于QCA9882的产品或优化现有无线网络的人来说，这份手册是不可或缺的工具。

80-Y0962-1 Rev. D 16 Confidential and Proprietary - Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

QCA9882 Dual-Band 2x2 MIMO 802.11ac/abgn WLAN SoC Data Sheet Functional Specification

The QCA9882 is comprised of several internal functional blocks, as summarized in Table 3-1.

Table 3-1 Functional blocks

Block Description

AXI The AXI bus is accessed simultaneously by multiple masters in the PCIE host memory, CPU

memory, and all programmable registers. The WLAN portion of the AXI fabric supports split

transactions to achieve higher utilization on the PCIE bus.

All register access from the CPU route through the AXI fabric. A bridge converts AXI requests

to AHB requests, and the AHB arbiter selects between PCIE register access requests and

CPU register access requests on a round-robin basis. All register accesses for all modules

including the MAC, CE, and blocks such as GPIOs, RTC, or OTP use the APB protocol. A

bridge converts AHB requests into APB. It must be noted here that the entire AXI fabric, AHB,

and APB interfaces all run synchronously on the SoC clock domain. See AXI.

CE The copy engine (CE) establishes a communication channel between the firmware and the

host. It performs a DMA copy from one memory location (source memory) to another memory

location (destination memory), and it can perform this DMA copy operation in a batch, under

control of software. A copy involves a read operation from the source memory, followed by a

write operation to the destination memory.

WLAN Clocking The MAC/baseband clock domain runs off of the WLAN PLL. The PLL runs at either at

160 MHz or 176 MHz. The CPU/SoC clock domain runs off of the CPU PLL. The AXI fabric

together with the AHB and APB buses typically run at either half or quarter CPU clock. The

PCIE clock domain runs at 125 MHz.

CPU Core and

Memory Controller

The CPU is a Tensilica XTENSA 7.0 processor with a hardware abstraction layer (HAL) to

support low level WLAN activity with minimal support from the PCIE host.

The CPU is configured with a peripheral interface (PIF). The outbound PIF is used by the CPU

for register access. The inbound PIF is used by the other AXI masters (MAC and CE) to

access the data memory (DMEM) connected to the CPU.

MAC/Baseband/RF The integrated 2.4/5 GHz 802.11ac MAC/baseband/radio includes the features of maximal

likelihood (ML) decoding, low-density parity check (LDPC), and maximal ratio combining

(MRC). The MAC includes a offload engine (OLE) block responsible for A-MSDU scatter and

gather, L2 header encapsulation and decapsulation, IP/TCP/UDP checksum, and Rx

classification.

PCIE Core All programmable registers can be accessed by either the PCIE host or by the internal CPU.

The PCIE core provides a simple proprietary low-bandwidth controller (LBC) interface for

PCIE Configuration

Space Registers

The QCA9882 PCIE configuration space maps to the host memory space. All programmable

registers can be accessed either by the PCIE host or by the internal CPU. The PCIE core

provides a simple proprietary low-bandwidth controller (LBC) interface for register accesses. A

bridge converts this LBC interface into standard AHB. An AHB-AHB bridge synchronizes the

clock domain from the PCIE clock domain to the SoC clock domain.

Some additional registers are accessible only by the PCIE host. These registers run on the

PCIE clock domain and are not routed through the main AHB arbiter. They allow the PCIE host

to determine the sleep status of the SoC and to wake up the SoC if needed. See PCIE

configuration space register descriptions.

WLAN AHB Arbiter Selects between the PCIE register access requests and CPU register access requests on a

round-robin basis.

WLAN GPIOs All digital pins map to 16 GPIOs. These GPIOs are used for a variety of purposes such as BT

coexistence, UART, I

C, SPI, JTAG. Another set of digital outputs are the four antenna

switches used as scan outputs during ATPG testing. The 16 GPIOs are divided into GPIOs

dedicated to BT and to WLAN, 8 to BT and 8 to WLAN. See GPI/GPIO.

WLAN OTP WLAN one-time programmable (OTP) memory

WLAN RTC The RTC block controls the clocks and power going to other modules within the chip. Its inputs

consist of sleep requests from these modules and its outputs consists of clock enable signals

used to gate the clocks going to these modules. The RTC block also manages resets going to

other modules within the device.

80-Y0962-1 Rev. D 17 Confidential and Proprietary - Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

QCA9882 Dual-Band 2x2 MIMO 802.11ac/abgn WLAN SoC Data Sheet Functional Specification

3.2 AXI

Figure 3-1 diagrams the AXI fabric.

Figure 3-2 AXI fabric diagram

Because PCIE host memory, CPU memory, and all programmable registers can all be accessed

simultaneously by multiple masters in the AXI bus, it is important to ensure that no address-related

conflicts arise. Upon booting, the PCIE host provides a unique base address (BAR) to all devices.

BAR location always aligns to the space requested by each device; in the QCA9882, it is 2 MBytes

of space, thus the BAR aligns to 2 MBytes and only bits [31:21] are non-zero. AXI fabric uses

these bits as input to steer incoming AXI requests to the appropriate slave. Note that BAR input to

the AXI fabric is not directly connected to the BAR value programmed by the PCIE host, but

comes from a programmable register. AXI fabric looks for BAR bits [31:21] for all incoming

transfers. See Table 3-3.

The Xtensa CPU memory address location must be in fixed address ranges: instruction memory

(IMEM) must be 8-12 MBytes (0x800000-0xBFFFFF) and data memory (DMEM) 4-8 MBytes

(0x400000-0x7FFFFF). Because these fixed address ranges could conflict with PCIE host memory

allocation, the an address translation mechanism is used for all CPU access. See Figure 3-4.

Figure 3-4 CPU address translation mechanism

All outbound transfers from the CPU pass through the address translation logic, which looks at the

MSB of the address (bit [31]). If this bit is low, the transfer is deemed to be a register access and

bits [31:21] of the address are appended with the BAR value. The AXI fabric steers the transfer to

the AXI-AHB bridge as indicated in Table 3-3. If bit [31] is high, the transfer is deemed as

intended to access PCIE memory, thus all but the MSB (bits [30:0]) must contain the intended

address in PCIE host memory. The programmable register PCIE_ADDR_31 contains the MSB of

the PCIE host memory location appended to the original address.

Table 3-3 Address decoding logic

Address Bits [31:21] Address Bits [20:0] AXI Slave Decode

BAR not matching — PCIE

BAR matching < 0x100000 AXI-AHB (register access)

> 0x100000 For the CPU, address bits [31:20] are replaced with the programmable

Mbyte address range matching with the CPU’s DMEM address space.

80-Y0962-1 Rev. D 20 Confidential and Proprietary - Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

QCA9882 Dual-Band 2x2 MIMO 802.11ac/abgn WLAN SoC Data Sheet Register Descriptions

4.1 Real-time clock registers

Table 4-3 summarizes the QCA9882 real-time clock registers and other configuration registers for

the SoC block.

Table 4-3 Real-Time Clock Register Summary

Address Name Description Page

0x00004000 SOC_RESET_CONTROL Reset Control page 22

0x00004020 SOC_CPU_CLOCK Clock Control for CPU page 23

0x00004028 SOC_CLOCK_CONTROL Clock Control for Functional Blocks page 23

0x00004030 SOC_WDT_CONTROL Watchdog Timer Control page 24

0x00004034 SOC_WDT_STATUS Watchdog Timer Status page 24

0x00004038 SOC_WDT Watchdog Timer page 24

0x0000403C SOC_WDT_COUNT Watchdog Timer Count page 25

0x00004040 SOC_WDT_RESET Watchdog Timer Reset page 25

0x00004044 SOC_INT_STATUS Interrupt Status for Local CPU Interrupts page 26

0x00004048 SOC_LF_TIMER0 Low-Frequency Timer page 27

0x0000404C SOC_LF_TIMER_COUNT0 Low-Frequency Timer Current Value page 27

0x00004050 SOC_LF_TIMER_CONTROL0 Clock Restart Policy and Reset for Low-

Frequency Timer

page 27

0x00004054 SOC_LF_TIMER_STATUS0 Low Frequency Timer Raw Interrupt Status page 28

0x00004058 SOC_LF_TIMER1 Low-Frequency Timer page 28

0x0000405C SOC_LF_TIMER_COUNT1 Low-Frequency Timer Current Value page 28

0x00004060 SOC_LF_TIMER_CONTROL1 Clock Restart Policy and Reset for Low-

Frequency Timer

page 29

0x00004064 SOC_LF_TIMER_STATUS1 Low Frequency Timer Raw Interrupt Status page 29

0x00004068 SOC_LF_TIMER2 Low-Frequency Timer page 30

0x0000406C SOC_LF_TIMER_COUNT2 Low-Frequency Timer Current Value page 30

0x00004070 SOC_LF_TIMER_CONTROL2 Clock Restart Policy and Reset for Low-

Frequency Timer

page 30

0x00004074 SOC_LF_TIMER_STATUS2 Low Frequency Timer Raw Interrupt Status page 31

0x00004078 SOC_LF_TIMER3 Low-Frequency Timer page 31

0x0000407C SOC_LF_TIMER_COUNT3 Low-Frequency Timer Current Value page 31

0x00004080 SOC_LF_TIMER_CONTROL3 Clock Restart Policy and Reset for Low-

Frequency Timer

page 32

0x00004084 SOC_LF_TIMER_STATUS3 Low Frequency Timer Raw Interrupt Status page 32

0x00004088 SOC_HF_TIMER High-Frequency Timer page 33

0x0000408C SOC_HF_TIMER_COUNT High-Frequency Timer Current Value page 33

0x00004090 SOC_HF_LF_COUNT Low-Frequency Timer Value Synchronous

with High-Frequency Timer Read

page 33

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