STM32U073微控制器：超低功耗与强大性能

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"STM32U073数据手册详细介绍了STM32U073x8/B/C系列微控制器，这些MCU具备高性能、低功耗的特点，适用于各种嵌入式应用。该系列芯片提供256 KB Flash存储器和40 KB SRAM，以及多种封装选项，包括UFQFPN、WLCSP、LQFP和UFBGA，引脚数量从32到81不等。STM32U073x器件集成了丰富的外设，如12位ADC、模拟比较器、运算放大器、RTC、定时器、电容感应通道、I2C、SPI、USART、低功耗UART以及无晶振USB2.0接口。此外，还包含一个带内部升压转换器的LCD控制器，可驱动不同尺寸的段码显示。" STM32U073系列微控制器是基于32位Arm Cortex-M0+内核的，运行频率可达56 MHz，内置了ART加速器以实现零等待状态的Flash执行。其低功耗特性显著，支持宽电源电压范围（1.71V to 3.6V），并能在各种低功耗模式下保持极低电流消耗，如VBAT模式下的130 nA（带有RTC和备份寄存器）、Shutdown模式的16 nA等。此外，它还具备快速唤醒能力，从Stop模式下可在4微秒内唤醒，并配备了棕色输出重置（BOR）功能，以确保系统稳定运行。在性能方面，STM32U073表现出色，Drystone2.1测试下达到1.13 DMIPS/MHz，CoreMark分数为134，ULPMark™-CP、-PP和-CM得分分别达到377、134和19.7，表明其在低功耗性能上尤为突出。内存配置包括最多256 KB的单银行Flash存储器，具有代码读取保护功能，以及40 KB的SRAM，带有硬件奇偶校验检查。模拟外设包括一个高速12位ADC（0.4 µs转换时间，可通过硬件过采样达到16位精度）、12位DAC输出通道和低功耗采样保持功能。通信接口方面，STM32U073支持多达21个电容感应通道，3个I2C，2个SPI，4个USART，2个低功耗UART，以及一个无晶振USB2.0接口，可用于设备模式。此外，该系列MCU的LCD控制器配备内部升压转换器，能够驱动8x48或4x52个段码的LCD显示，使得STM32U073成为需要高效能、低功耗和丰富外设集成的嵌入式应用的理想选择，如物联网设备、智能家居、便携式医疗设备、工业控制等。

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory.

• System clock source: two different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock

to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to

system PLL.

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies form

100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI

frequency can be automatically trimmed by hardware to reach an accuracy better than ± 0.25%. The

MSI can supply a PLL.

– System PLL, which can be fed by HSE, HSI16 or MSI. It provides a system clock up to 56 MHz.

• Auxiliary clock source: three ultra-low-power clock sources for the real-time clock (RTC), and the LCD

controller:

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes.

The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ± 5% accuracy, also used to clock an independent

watchdog.

• Peripheral clock sources: several peripherals (RNG, USARTs, I2Cs, LPTIMs, ADC) have their own clock

independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically

switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected

and generate an interrupt. The CSS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for external use by the

application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT

operation).

Several prescalers enable the application to configure AHB and APB domain clock frequencies, 56 MHz at

maximum.

3.10

Clock recovery system (CRS)

The STM32U073x8/B/C devices embed a special block, which enables automatic trimming of the internal 48 MHz

oscillator, to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is

based on the external synchronization signal, which could be either derived from USB SOF signalization, from

LSE oscillator, from an external signal on CRS_SYNC pin, or generated by the user software. For faster lock-in

during startup, it is also possible to combine automatic trimming with manual trimming action.

3.11

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital

or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious

writing to I/O control registers.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 1

page 16/145

3.12 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With seven channels, it performs data transfers between memory-mapped peripherals and/or memories, to

offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes

an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-peripheral data

transfers

• Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and

AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a

software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (four levels per channel: very high, high,

medium, low) and by hardware in case of equality (such as request to channel 1 has priority over

request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing

and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2

- 1

• Generation of an interrupt request per channel. Each interrupt request originates from any of the three

DMA events: transfer complete, half transfer, or transfer error.

3.13

DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA

controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its

DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable

events on its input trigger signals.

3.14

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The

Cortex

-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event

controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events

such as, for example, a division by zero and, core-external events such as logical level changes on physical lines.

Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the

original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and

unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt

service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-

multiple and store-multiple operations significantly increases the device’s responsiveness in processing

exceptions.

3.14.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line

events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex

-M0+ exceptions. It

provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and

start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the

NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base

address and the ISR order number used as offset.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 1

page 17/145

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for

being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-

chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary

processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

• Low-latency interrupt processing

• Four priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying

wake-up events at processor wake-up from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge

detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which enables the software to identify the

origin of the processor wake-up from Stop mode or, to identify the GPIO and the edge event having caused an

interrupt.

3.15

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator

polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the

scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC

calculation unit helps compute a signature of the software during runtime, to be compared with a reference

signature generated at link time and stored at a given memory location.

3.16

Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32U073x8/B/C devices. It can be extended to 16-

bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels

(temperature sensor, voltage reference, V

BAT

monitoring). It performs conversions in single-shot or scan mode. In

scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 Msps even

with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the

active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V

supply range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to

AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned

channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers,

to allow the application to synchronize A/D conversions with timers.

3.16.1 Temperature sensor

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital

value.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 1

page 18/145

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature

measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the

uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factory-calibrated by ST. The

resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

Table 5. Temperature sensor calibration values

Calibration value

name

Description Memory address

TS_CAL1

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 6E68 - 0x1FFF 6E69

TS_CAL2

TS ADC raw data acquired at a

temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 6E8A - 0x1FFF 6E8B

3.16.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the ADC and

comparators. V

REFINT

is internally connected to an ADC input. The V

REFINT

voltage is individually precisely

measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in

read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value

name

Description Memory address

REFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 6EA4 - 0x1FFF 6EA5

3.16.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using an internal

ADC input. As the V

BAT

voltage may be higher than V

DDA

and thus outside the ADC input range, the V

BAT

pin is

internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the

BAT

voltage.

3.17

Digital-to-analog converter (DAC)

The single-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel

output. The architecture of either channel is based on integrated resistor string and an inverting amplifier.

Features of the DAC:

• One DAC output channel

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

STM32U073x8/B/C

Functional overview

DS14548 - Rev 1

page 19/145

3.18 Voltage reference buffer (VREFBUF)

When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC)

and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer

is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA

pin and so the internal voltage reference buffer cannot be used.

3.19

Comparators (COMP)

STM32U073x8/B/C embed two embedded rail-to-rail analog comparators with programmable reference voltage

(internal or external), hysteresis, speed (low for low-power), and output polarity.

The reference voltage can be one of the following:

• External, from an I/O

• Internal, from DAC

• Internal reference voltage (V

REFINT

) or its submultiple (1/4, 1/2, 3/4)

The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers

and can be also combined into a window comparator.

3.20 Operational amplifier (OPAMP)

The STM32U073x8/B/C devices embed one operational amplifier with external and internal follower routing and

PGA capability.

Features of the operational amplifier:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.21

Liquid crystal controller (LCD)

The LCD drives up to eight common terminals and 48 segment terminals to drive up to 352 pixels.

Features of the LCD:

• Internal step-up converter to guarantee functionality and contrast control irrespective of V

. This converter

can be deactivated, in which case the V

LCD

pin is used to provide the voltage to the LCD

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Up to eight pixels can be programmed to blink

Unneeded segments and common pins can be used as general I/O pins

LCD RAM can be updated at any time owing to a double-buffer

The LCD controller can operate in Stop mode

3.22

True random-number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit

samples. It is composed of a live entropy source (analog) and an internal conditioning component.

3.23

Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic timers, three low-power

timers, two watchdog timers and a SysTick timer.

Table 7 compares features of the advanced-control, general-

purpose and basic timers.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 1

page 20/145

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