W25N01GV: 1GB Serial SLC NAND Flash Memory with SPI Interface

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W25N01GV是一款1GB的串行单层电荷存储器(NAND Flash)，针对空间有限、引脚和功耗敏感的系统提供了高效能的存储解决方案。该系列采用流行的SPI接口，结合大容量非易失性内存特性，适用于多种应用场景，如代码镜像到RAM、在双/四线SPI(XIP)模式下执行代码以及存储语音、文本和数据。这款Flash内存工作在2.7V至3.6V电压范围，具有极低的功耗，包括25mA的活动电流和10μA的待机模式。W25N01GV系列采用了紧凑型封装，如WSON 8x6毫米和SOIC 300-mil，这些在过去对于传统NAND闪存来说是难以实现的。产品还支持多种球栅阵列(TFBGA)封装选项，如8x6毫米的5x5或6x4球阵列。 W25N01GV的特点包括内置的双/四线SPI缓冲读取功能以及连续读写能力，确保了高效的数据传输。其引脚配置详细描述了Chip Select(/CS)用于选择操作地址，Serial Data Input/Output (DI/DO)与IO0, IO1, IO2, IO3提供数据传输，WriteProtect(/WP)用于防止误写，HOLD(/HOLD)控制数据保持，以及Serial Clock (CLK)同步数据传输。设备的操作流程分为标准SPI、双SPI和四SPI指令集，每种模式都支持不同的数据传输速率和功能。此外，W25N01GV还具备Hold功能，可以在数据传输期间暂时保持状态。保护、配置和状态寄存器也是一大亮点，包括一个可编程的保护/状态寄存器，既可进行数据保存，又可锁定防止未经授权的访问。 W25N01GV是一款高性能、低功耗的NAND Flash解决方案，特别适合对存储空间、引脚数和功耗有严格要求的现代电子系统设计。通过灵活的封装和丰富的功能，它能有效提高系统的稳定性和效率。

W25N01GVxxIG/IT

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5. BLOCK DIAGRAM

Figure 2. W25N01GV Flash Memory Architecture and Addressing

Page

Structure

(2,112-Byte)

Sector 0

512-Byte

Sector 1

512-Byte

Sector 2

512-Byte

Sector 3

512-Byte

Spare 0

16-Byte

Spare 1

16-Byte

Spare 2

16-Byte

Spare 3

16-Byte

Column

Address

000h -- 1FFh 200h -- 3FFh 400h -- 5FFh 600h -- 7FFh 800h -- 80Fh 810h -- 81Fh 820h -- 82Fh 830h -- 83Fh

Byte

Definition

Bad Block

Marker

User Data

ECC for

Sector 0

ECC for

Spare

Byte

Address

0123456789ABCDEF

Main Memory Array (2,048-Byte)

ECC Protected

Spare Area (64-Byte)

No ECC

Protection

ECC

Protected

ECC for

Byte 4 to Byte D

1,024 Blocks X 64 Pages

(65,536 Pages)

Page Address PA[15:0]

AddressBits 313029282726252423222120191817161514131211109876543210

SpiFlash(upto128M‐Bit) XXXXXXXX

SpiFlash(upto32G‐Bit)

XXXX

XXXX Ext

SerialNAND(1G‐Bit)

PageAddress(PA)[15:0] ColumnAddress(CA)[11:0]

128KBBlockAddr(1024Blocks) PageAdd r(64Pages) ByteAddress(0‐2047Byte)

64KBBlockAddr (256Blocks) PageAd dr ess(256Pages) ByteAddress(0‐255Byte)

64KBBlockAddress PageAddress(256Pages) ByteAddress

(0‐255Byte)

W25N01GVxxIG/IT

Publication Release Date: March 21, 2016

- 12 - Revision G

6. FUNCTIONAL DESCRIPTIONS

6.1 Device Operation Flow

Figure 3. W25N01GV Flash Memory Operation Diagram

6.1.1 Standard SPI Instructions

The W25N01GV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI

input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO

output pin is used to read data or status from the device on the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising

edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2 Dual SPI Instructions

The W25N01GV supports Dual SPI operation when using instructions such as “Fast Read Dual Output

(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device

at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for

quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical

Power Up

(default BUF=1, ECC-E=1)

Initialization &

Default Page Load (00) ~500us

Load Page xx

tRD ~50us

Start “Buffer Read” with column address

(Page 00 or Page xx)

Read

page 00?

Set BUF=0

Load Page yy

tRD ~50us

Start “Continuous Read” from column 0

(Page yy)

Power Up

(default BUF=0, ECC-E=1)

Initialization &

Default Page Load (00) ~500us

Load Page xx

tRD ~50us

Start “Continuous Read” from column 0

(Page 00 or Page xx)

Read

page 00?

Set BUF=1

Load Page yy

tRD ~50us

Start “Buffer Read” with column address

(Page yy)

W25N01GVxxIG W25N01GVxxIT

W25N01GVxxIG/IT

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code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become

bidirectional I/O pins: IO0 and IO1.

6.1.3 Quad SPI Instructions

The W25N01GV supports Quad SPI operation when using instructions such as “Fast Read Quad Output

(6Bh)”, “Fast Read Quad I/O (EBh)” and “Quad Program Data Load (32h/34h)”. These instructions allow

data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad

Read instructions offer a significant improvement in continuous and random access transfer rates allowing

fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI

instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become

IO2 and IO3 respectively.

6.1.4 Hold Function

For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N01GV operation to be paused

while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI

data and clock signals are shared with other devices. For example, consider if the page buffer was only

partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can

save the state of the instruction and the data in the buffer so programming can resume where it left off once

the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation,

not during Quad SPI. When a Quad SPI command is issued, /HOLD pin will act as a dedicated IO pin (IO3).

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on

the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD

condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising

edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition

will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is

high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS)

signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal

logic state of the device.

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