OpenRISC 1200 IP核规格初步草案：修订与更新

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OpenRISC1200 IP Core Specification (Preliminary Draft) 是一份详细介绍了OpenRISC 1200微处理器核心架构的规格文档，该文档由Damjan Lampret和Julius Baxter共同编撰，历经多个版本的修订和完善。这份规格文件旨在提供关于OpenRISC 1200处理器的全面技术细节，包括但不限于硬件设计、指令集、架构特性、功能描述以及修订历史。在"REVISION HISTORY"部分，我们可以看到文档从v0.1版本开始，初始草案由Damjan Lampret于2001年3月28日发布，随后经过多次迭代，如v0.2版本中第一次正式出版，v0.3版本完成大部分章节并修复了一些隐藏的错误，等待反馈以进行更新。随着与OR1K架构手册的同步（v0.4），文档进一步完善，特别是在v0.5版本中解决了已知的问题。值得注意的是，v0.6版本对特殊处理寄存器（SPR）地址进行了调整，而在v0.7版本中，调试单元被简化以提高性能。到了v0.8版本，文档增加了关于浮点处理单元（FPU）实现、数据缓存写回能力的信息，以及处理器输入时钟的详细描述。此外，还对参考文档进行了更新，特别是指令执行阶段周期表，增加了除法操作周期，并对conﬁguration registers（配置寄存器）中的位进行了相应调整，以保持与最新OR1200规范的兼容性。 v0.9版本进一步澄清了支持的OR1K指令集部分，明确了核心功能的明确边界，修复了核心时钟输入信息和指令执行阶段周期表的表述，提升了文档的精确性和一致性。通过这份OpenRISC1200 IP Core Specification，用户可以了解到这款处理器的核心特性和设计决策，对于嵌入式系统开发者来说，这是一份至关重要的参考资料，能够帮助他们理解和优化基于OpenRISC 1200架构的应用程序。随着文档的不断更新，它反映了OpenRISC社区对技术演进的持续关注和努力。

OpenRISC 1200 IP Core Speciﬁcation

(Preliminary Draft)

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Chapter 2

Architecture

Figure 2.1 below shows general architecture of OR1200 IP core. It consists of several building blocks:

• CPU/FPU/DSP central block

• Direct-mapped data cache

• Direct-mapped instruction cache

• Data MMU based on hash based DTLB

• Instruction MMU based on hash based ITLB

• Power management unit and power management interface

• Tick timer

• Debug unit and development interface

• Interrupt controller and interrupt interface

• Instruction and Data WISHBONE host interfaces

Figure 2.1: Core’s Architecture

OpenRISC 1200 IP Core Speciﬁcation

(Preliminary Draft)

4 / 49

2.1 CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor. Figure 2.2 shows basic block diagram of the CPU/DSP. Not

pictured are the FPU components. OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction

set. No ORBIS64, ORFBX64 or ORVDX64 instructions are implemented in OR1200.

Figure 2.2: CPU/FPU/DSP Block Diagram

2.1.1 Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them

to available execution units, and maintains a state history to ensure a precise exception model and that operations ﬁnish in order.

It also executes conditional branch and unconditional jump instructions.

The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution

unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all

ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

2.1.2 General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of

register ﬁle to implement fast switching between working contexts, however this feature is not implemented in current OR1200

implementation.

OR1200 implements general-purpose register ﬁle as two synchronous dual-port memories with capacity of 32 words by 32 bits

per word.

2.1.3 Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU’s internal bus. It is implemented as an independent

execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.

The following are LSU’s main features:

• all load/store instruction implemented in hardware (atomic instructions included)

• address entry buffer

• pipelined operation

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