1390 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 10, OCTOBER 2018
A 1-to-1-kHz, 4.2-to-544-nW, Multi-Level
Comparator Based Level-Crossing ADC
for IoT Applications
Yuting Hou, Student Member, IEEE, Khalil Yousef, Member, IEEE, Mohamed Atef , Senior Member, IEEE,
Guoxing Wang
, Senior Member, IEEE, and Yong Lian, Fellow, IEEE
Abstract—This brief presents the design of an ultra-low power
level-crossing analog-to-digital converter (LC-ADC) for IoT and
biomedical applications. The proposed LC-ADC utilizes only one
multi-level comparator instead of multiple comparators as in
conventional LC-ADC, leading to simplified implementation and
significant reduction in power. Implemented in 0.18-µmCMOS
process, the LC-ADC achieves 7.9 equivalent number of bits with
a 49 dB signal-to-noise and distortion ratio at the input frequency
up to 1 kHz. The measured minimum power is only 4.2 nW at
the supply voltage of 0.55 V.
Index Terms—LC-ADC, multi-level comparator, ultra-low
power.
I. INTRODUCTION
S
IGNALS in Internet-of-Things (IoT) and healthcare appli-
cations are often sporadic due to time-varying activities.
Using Nyquist analog-to-digital converter (ADC) to handle
such signals may result in significant power waste when the
input signal varies slowly, i.e., the signal frequency is much
lower than Nyquist frequency. It was shown [1] that level-
crossing ADC is much more energy efficient in handling such
signals.
Different from conventional Nyquist ADC that samples sig-
nal at fixed frequency, the level-cross ADC samples the signal
at pre-determined change of amplitude [1]. The operations of
Nyquist ADC and LC-ADC are demonstrated in Fig. 1.It
is clear that Nyquist ADC divides X-axis (time) into equal
interval while LC-ADC divides Y-axis (amplitude) into equal
interval. Since LC-ADC is based on the change of amplitude,
its power consumption is related to the activities in the input
signal. When the change in signal is absent or very slow, the
Manuscript received June 27, 2018; accepted June 28, 2018. Date of publi-
cation July 16, 2018; date of current version September 27, 2018. This work
was supported in part by the Natural Science Foundation of China under
Grant 61474074, and in part by the National Key Research and Development
Program of China under Grant 2016YFE0116900. This brief was recom-
mended by Associate Editor J. M. de la Rosa. (Corresponding author:
Guoxing Wang.)
Y. Hou, G. Wang, and Y. Lian are with the Bio-Circuits and Systems
Laboratory, Department of Micro-Nano Electronics, Shanghai Jiao Tong
University, Shanghai 200240, China (e-mail: guoxing@sjtu.edu.cn).
K. Yousef and M. Atef are with the Bio-Circuits and Systems Laboratory,
Department of Micro-Nano Electronics, Shanghai Jiao Tong University,
Shanghai 200240, China, and also with the Electrical Engineering Department,
Assiut University, Asyut 71718, Egypt (e-mail: kyousef@aun.edu.eg;
moh_atef@aun.edu.eg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2018.2854862
(a)
(b)
Fig. 1. (a) Nyquist sampling. (b) Level crossing sampling.
LC-ADC generates no sample or few samples resulting in sig-
nificant savings in power. Typical applications of LC-ADC
are signals from human body, environmental changes, food
production, building structure, etc.
To perform level crossing sampling, a straightforward way
is to use N comparators [2], which is similar to Nyquist
based flash ADCs but without the need of sampling clocks.
However its power consumption is high due to the use of large
number of comparators. To reduce the power consumption,
two-comparator approach was proposed in [3] to implement
the LC-ADC, as shown in Fig. 2. Further power saving is pos-
sible if the n-bit digital-to-analog converter (DAC) is replaced
by an 1-bit DAC [4]. Till now, all LC-ADC implementations
require at least two comparators to detect the change in ampli-
tude. These comparators usually consume more than 50 % of
the LC-ADC power [4]–[6].
In this brief, we propose a new LC-ADC architecture that
utilizes only one multi-level comparator to fulfill the level
crossing detection, thus reduces the power consumption com-
pared to two-comparator approaches. The architecture and the
circuit implementation are discussed in Section II. Section III
1549-7747
c
2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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