高速MOSFET栅极驱动电路设计解析

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"功率MOSFET的驱动电路设计.pdf" 本文主要探讨的是高效率功率MOSFET门极驱动电路的设计与应用指南，由Laszlo Balogh撰写。其目的是提供一个系统的方法来设计用于高速开关应用的高性能门极驱动电路，适合各个经验层次的电力电子工程师参考。该文深入剖析了最常见的设计挑战，提供了“一站式”的解决方案。在本文中，作者分析了最常用的电路方案及其性能，同时考虑了寄生组件的影响、瞬态以及极端工作条件下的表现。讨论从MOSFET技术的基础和开关操作概述开始，逐步过渡到更复杂的问题。具体涵盖了以下内容： 1. MOSFET技术基础：MOSFET（金属氧化物半导体场效应晶体管）的基本原理和开关操作，这是理解门极驱动电路设计的基础。 2. 地参考和高压侧门极驱动电路设计：详细介绍了这两种驱动电路的设计过程，包括其各自的优势和限制。 3. 交流耦合和变压器隔离解决方案：针对不同应用场景，解释了如何实现电气隔离和信号传输，确保驱动电路的安全性和稳定性。 4. 同步整流器应用中的MOSFET门极驱动要求：这部分专门讨论了在同步整流器中，MOSFET特有的门极驱动需求，这对于提高电源转换效率至关重要。 5. 数值设计示例：通过一系列逐步的数值设计实例，进一步阐述了理论知识在实际设计中的应用，帮助读者更好地理解和应用文中所介绍的概念。在设计高速MOSFET门极驱动电路时，必须考虑的关键因素包括驱动电压的上升和下降时间、驱动电流的大小、驱动电阻的选择、以及防止振荡和电磁干扰的措施。此外，对瞬态响应的控制是确保MOSFET快速、无损开关的关键，这涉及到正确处理寄生电感和电容的影响。这份设计指南不仅提供了理论知识，还强调了实践经验，对于从事电力电子领域，尤其是涉及MOSFET驱动电路设计的工程师来说，是一份非常宝贵的参考资料。通过学习和应用其中的方法，工程师可以更好地优化电路性能，提升系统的可靠性和效率。

2-7

This is accomplished by charging the C

and

capacitors, thus gate current is now split

between the two components. While these

capacitors are being charged, the drain current is

still constant, and the drain-to-source voltage is

slightly decreasing as the on-resistance of the

device is being reduced.

B. Turn-Off Procedure

The description of the turn-off procedure for

the MOSFET transistor is basically back tracking

the turn-on steps from the previous section. Start

with V

being equal to V

DRV

and the current in

the device is the full load current represented by

in Fig. 3. The drain-to-source voltage is

being defined by I

and the R

DS(on)

of the

MOSFET. The four turn-off steps are shown in

Fig. 5. for completeness.

DRV

GATE

G,I

3 421

Fig. 5. MOSFET turn-off time intervals

The first time interval is the turn-off delay

which is required to discharge the C

ISS

capacitance from its initial value to the Miller

plateau level. During this time the gate current is

supplied by the C

ISS

capacitor itself and it is

flowing through the C

and C

capacitors of

the MOSFET. The drain voltage of the device is

slightly increasing as the overdrive voltage is

diminishing. The current in the drain is

unchanged.

In the second period, the drain-to-source

voltage of the MOSFET rises from I

⋅R

DS(on)

the final V

DS(off)

level, where it is clamped to the

output voltage by the rectifier diode according to

the simplified schematic of Fig. 3. During this

time period – which corresponds to the Miller

plateau in the gate voltage waveform - the gate

current is strictly the charging current of the C

capacitor because the gate-to-source voltage is

constant. This current is provided by the bypass

capacitor of the power stage and it is subtracted

from the drain current. The total drain current

still equals the load current, i.e. the inductor

current represented by the DC current source in

Fig. 3.

The beginning of the third time interval is

signified by the turn-on of the diode, thus

providing an alternative route to the load current.

The gate voltage resumes falling from V

GS,Miller

to V

. The majority of the gate current is

coming out of the C

capacitor, because the C

capacitor is virtually fully charged from the

previous time interval. The MOSFET is in linear

operation and the declining gate-to-source

voltage causes the drain current to decrease and

reach near zero by the end of this interval.

Meanwhile the drain voltage is steady at V

DS(off)

due to the forward biased rectifier diode.

The last step of the turn-off procedure is to

fully discharge the input capacitors of the device.

is further reduced until it reaches 0V. The

bigger portion of the gate current, similarly to the

third turn-off time interval, supplied by the C

capacitor. The drain current and the drain voltage

in the device are unchanged.

2-8

Summarizing the results, it can be concluded

that the MOSFET transistor can be switched

between its highest and lowest impedance states

(either turn-on or turn-off) in four time intervals.

The lengths of all four time intervals are a

function of the parasitic capacitance values, the

required voltage change across them and the

available gate drive current. This emphasizes the

importance of the proper component selection

and optimum gate drive design for high speed,

high frequency switching applications.

Characteristic numbers for turn-on, turn-off

delays, rise and fall times of the MOSFET

switching waveforms are listed in the transistor

data sheets. Unfortunately, these numbers

correspond to the specific test conditions and to

resistive load, making the comparison of

different manufacturers’ products difficult. Also,

switching performance in practical applications

with clamped inductive load is significantly

different from the numbers given in the data

sheets.

C. Power Losses

The switching action in the MOSFET

transistor in power applications will result in

some unavoidable losses, which can be divided

into two categories.

The simpler of the two loss mechanisms is

the gate drive loss of the device. As described

before, turning-on or off the MOSFET involves

charging or discharging the C

ISS

capacitor. When

the voltage across a capacitor is changing, a

certain amount of charge has to be transferred.

The amount of charge required to change the

gate voltage between 0V and the actual gate

drive voltage V

DRV

, is characterized by the

typical gate charge vs. gate-to-source voltage

curve in the MOSFET datasheet. An example is

shown in Fig. 6.

This graph gives a relatively accurate worst

case estimate of the gate charge as a function of

the gate drive voltage. The parameter used to

generate the individual curves is the drain-to-

source off state voltage of the device. V

DS(off)

influences the Miller charge – the area below the

flat portion of the curves – thus also, the total

gate charge required in a switching cycle. Once

the total gate charge is obtained from Fig. 6, the

gate charge losses can be calculated as:

DRVGDRVGATE

fQVP ⋅⋅=

where V

DRV

is the amplitude of the gate drive

waveform and f

DRV

is the gate drive frequency –

which is in most cases equal to the switching

frequency. It is interesting to notice that the

⋅f

DRV

term in the previous equation gives the

average bias current required to drive the gate.

The power lost to drive the gate of the

MOSFET transistor is dissipated in the gate

drive circuitry. Referring back to Figures 4 and

5, the dissipating components can be identified

as the combination of the series ohmic

impedances in the gate drive path. In every

switching cycle the required gate charge has to

pass through the driver output impedances, the

external gate resistor, and the internal gate mesh

resistance. As it turns out, the power dissipation

is independent of how quickly the charge is

delivered through the resistors. Using the resistor

designators from Figures 4 and 5, the driver

power dissipation can be expressed as:

OFFDRV,ONDRV,DRV

IG,GATELO

DRVGDRVLO

OFFDRV,

IG,GATEHI

DRVGDRVHI

ONDRV,

PPP

RRR

fQVR

RRR

fQVR

⋅⋅⋅

⋅=

⋅⋅⋅

⋅=

Vgs, Gate-to-Source Voltage (V)

Qg, Total Gate Charge (nC)

DRV

Fig. 6. Typical gate charge vs. gate-to-source

voltage.

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