Philips SAA7111A: Enhanced Video Input Processor 数据手册

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"SAA7111A是Philips Semiconductors生产的一款增强型视频输入处理器（EVIP）。这款集成电路主要用于视频解码，具备多种处理功能，包括模拟输入处理、色度处理、亮度处理、RGB矩阵等。" SAA7111A是一款集成度很高的芯片，适用于各种视频处理应用。以下是关于该器件的详细知识点： 1. **特点（FEATURES）**：SAA7111A的主要特点可能包括高精度视频信号处理、灵活的增益控制、VBI数据旁路、数字输出（VPO总线）、以及支持线-21数据的文本切片器等功能。 2. **应用场景（APPLICATIONS）**：这款芯片常用于电视接收机、视频录像机、卫星接收机等设备，处理视频信号的解码和优化，以提供高质量的视频输出。 3. **概述（GENERAL DESCRIPTION）**：SAA7111A是一个增强型视频输入处理器，设计用于处理模拟视频信号，包括色度和亮度信号的分离与处理，同时具备对垂直消隐期间数据（VBI）的处理能力。 4. **快速参考数据（QUICK REFERENCEDATA）**：这部分可能包含了芯片的关键电气参数和性能指标，如工作电压、电流消耗、带宽等。 5. **订购信息（ORDERING INFORMATION）**：提供了如何订购SAA7111A芯片的相关细节，包括封装类型、订货代码等。 6. **模块图（BLOCK DIAGRAM）**：展示了芯片内部各个功能模块的结构，帮助用户理解其工作原理。 7. **引脚配置（PINNING）**：列出了芯片的所有引脚及其功能，指导用户正确连接和使用。 8. **功能描述（FUNCTIONAL DESCRIPTION）**：详细介绍了每个功能模块的工作原理，包括模拟输入处理、电平钳位、增益控制、色度和亮度处理、RGB矩阵转换、VBI数据旁路、数字输出、同步信号处理、时钟生成电路、上电复位和CE输入、RTCO输出，以及线-21文本切片器。 9. **边界扫描测试（BOUNDARY-SCAN TEST）**：SAA7111A支持边界扫描测试，这是一种用于检测芯片内部连接和功能的调试技术，包括初始化和设备识别代码。 10. **增益图表（GAIN CHARTS）**：显示了不同设置下的增益特性，帮助用户调整信号处理的增益。 11. **极限值（LIMITING VALUES）**：给出了芯片在不同条件下的工作极限，以确保安全和稳定运行。 12. **特性（CHARACTERISTICS）**：列出了芯片的典型电气特性，如输入/输出电压、电流、噪声等。 13. **时序图（TIMING DIAGRAMS）**：提供了芯片内部操作的时间关系，有助于理解和调试系统级的同步问题。 14. **C**：这部分可能包含的是英文原文的继续，但在此处提供的信息不完整。 SAA7111A是一个功能强大的视频处理芯片，它集成了多个处理单元，可以有效地对模拟视频信号进行解码和处理，适用于多种视频系统。

1998 May 15 12

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The output data formats are controlled via the I

C-bus bits

OFTS0, OFTS1 and RGB888. Timing for the data stream

formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit),

RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit)

with an LLC2 data rate, is achieved by marking each

second positive rising edge of the clock LLC in conjunction

with CREF (clock reference) (except RGB (8, 8 and 8),

see special application in Fig.32). The higher output

signals VPO15 to VPO8 in the YUV format perform the

digital luminance signal. The lower output signals

VPO7 to VPO0 in the YUV format are the bits of the

multiplexed colour difference signals (B − Y) and (R − Y).

The arrangement of the RGB (5, 6 and 5) and

RGB (8, 8 and 8) data stream bits on the VPO-bus is given

in Table 6.

The data stream format YUV 4:2:2 (the 8 higher output

signals VPO15 to VPO8) in LLC data rate fulfils the

CCIR-656 standard with its own timing reference code at

the start and end of each video data block.

A pixel in the format tables is the time required to transfer

a full set of samples. If 16-bit 4 : 2 : 2 format is selected

two luminance samples are transmitted in comparison to

one (B − Y) and one (R − Y) sample within a pixel.

The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEI to LOW.

The signal is used to control fast switching on the digital

VPO-bus. HIGH on this pin forces the VPO outputs to a

high-impedance state (see Figs 18 and 19). The I

C-bus

bit OEYC has to be set HIGH to use this function.

The digitized PAL, SECAM or NTSC signals AD1 (7 to 0)

and AD2 (7 to 0) are connected directly to the VPO-bus

via I

C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.

AD1 (7 to 0) → VPO (15 to 8) and

AD2 (7 to 0) → VPO (7 to 0).

The selection of the analog input channels is controlled via

C-bus subaddress 02 MODE select.

The upsampled 8-bit offset binary CVBS signal (VBI-data

bypass) is multiplexed under control of the I

C-bus to the

digital VPO-bus (see Fig.8).

8.8 Reference signals HREF, VREF and CREF

• HREF: The positive slope of the HREF output signal

indicates the beginning of a new active video line.

The high period is 720 luminance samples long and is

also present during the vertical blanking.

The description of timing and position from HREF is

illustrated in Figs 15, 16, 21 and 23.

• VREF: The VREF output delivers a vertical reference

signal or an inverse composite blank signal controlled

via the I

C-bus [subaddress 11, inverse composite

blank (COMPO)]. Furthermore four different modes of

vertical reference signals are selectable via the I

C-bus

[subaddress 13, vertical reference output control

(VCTR1 and VCTR0)]. The description of VREF timing

and position is illustrated in Figs 15, 16, 24 and 25.

• CREF: The CREF output delivers a clock/pixel qualifier

signal for external interfaces to synchronize to the

VPO-bus data stream.

Four different modes for the clock qualifier signal are

selectable via the I

C-bus [subaddress 13, clock

reference output control (CCTR1 and CCTR0)].

The description of CREF timing and position is

illustrated in Figs 16, 18, 20 and 21.

8.9 Synchronization

The prefiltered luminance signal is fed to the

synchronization stage. Its bandwidth is reduced to 1 MHz

in a low-pass filter. The sync pulses are sliced and fed to

the phase detectors where they are compared with the

sub-divided clock frequency. The resulting output signal is

applied to the loop filter to accumulate all phase

deviations. Internal signals (e. g. HCL and HSY) are

generated in accordance with analog front-end

requirements. The output signals HS, VS, and PLIN are

locked to the timing reference, guaranteed between the

input signal and the HREF signal, as further improvements

to the circuit may change the total processing delay. It is

therefore not recommended to use them for applications

which require absolute timing accuracy on the input

signals. The loop filter signal drives an oscillator to

generate the line frequency control signal LFCO

(see Fig.7).

8.10 Clock generation circuit

The internal CGC generates all clock signals required for

the video input processor. The internal signal LFCO is a

digital-to-analog converted signal provided by the

horizontal PLL. It is the multiple of the line frequency

Internally the LFCO signal is multiplied by a factor of 2 or 4

in the PLL circuit (including phase detector, loop filtering,

VCO and frequency divider) to obtain the LLC and LLC2

output clock signals. The rectangular output clocks have

a 50% duty factor (see Fig.26).

6.75MHz

429

432

----------

×=

1998 May 15 13

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8.11 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply

voltages (below 2.7 V) will initiate the reset sequence; all

outputs are forced to 3-state. The indicator output RES is

LOW for approximately 128LLC after the internal reset and

can be applied to reset other circuits of the digital TV

system.

It is possible to force a reset by pulling the chip enable

(CE) to ground. After the rising edge of CE and sufficient

power supply voltage, the outputs LLC, LLC2, CREF,

RTCO, RTS0, RTS1, GPSW and SDA return from 3-state

to active, while HREF, VREF, HS and VS remain in 3-state

and have to be activated via I

C-bus programming

(see Table 5).

8.12 RTCO output

The real time control and status output signal contains

serial information about the actual system clock

(increment of the HPLL), subcarrier frequency [increment

and phase (via reset) of the FSC-PLL] and PAL sequence

bit. The signal can be used for various applications in

external circuits, e.g. in a digital encoder to achieve clean

encoding (see Fig.20).

8.13 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed

Captioning data from a 525-line CVBS signal. Extended

data services on Line-21 Field 2 are also supported.

If valid data is detected the two data bytes are stored in two

C-bus registers. A parity check is also performed and the

result is stored in the MSB of the corresponding byte.

A third I

C-bus register is provided for data valid and data

ready flags. The two bits F1VAL and F2VAL indicate that

the input signal carries valid Closed Captioning data in the

corresponding fields. The data ready bits F1RDY and

F2RDY have to be evaluated if asynchronous I

C-bus

reading is used.

8.13.1 S

UGGESTIONS FOR I

C-BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21 DATA

There are two methods by which the software can acquire

the data:

1. Synchronous reading once per frame (or once per

field); It can use either the rising edge (Line-21 Field 1)

or both edges (Line-21 Field 1 or 2) of the ODD signal

(pin RTSO) to initiate an I

C-bus read transfer of the

three registers 1A, 1B and 1C.

2. Asynchronous reading; It can poll either the F1RDY bit

(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21

Field 1 or 2). After valid data has been read the

corresponding F*RDY bit is set to LOW until new data

has arrived. The polling frequency has to be slightly

higher than the frame or field frequency, respectively.

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