赛灵思V5 FPGA配置指南

需积分: 9 113 浏览量更新于2024-07-26 1 收藏 3.11MB PDF 举报

"赛灵思V5系列FPGA的用户手册，是官方发布的英文版文档，主要针对Virtex-5 FPGA的配置与开发提供指导，适用于选择和使用Xilinx产品。" 赛灵思V5系列FPGA是Xilinx公司推出的一系列高性能、可编程逻辑器件，广泛应用于通信、计算、图像处理等多个领域。该用户手册是开发者进行Virtex-5 FPGA设计的关键参考资料，详细介绍了如何配置和使用这些芯片。在手册中，你将找到以下关键知识点： 1. **配置流程**：手册会详细介绍Virtex-5 FPGA的配置流程，包括配置模式（如JTAG、SPI、Parallel等）、配置设备的选择以及配置文件的生成。理解这一过程对于正确地将设计加载到FPGA中至关重要。 2. **设计输入与综合**：Xilinx的VHDL或Verilog HDL语言是设计的基础，手册会涵盖如何使用Xilinx的工具（如ISE Design Suite）进行设计输入、综合及仿真，确保设计的正确性。 3. **时序分析与优化**：为了满足速度和功耗要求，手册会讲解如何进行时序分析，并提供方法优化设计以达到最佳性能。 4. **I/O接口**：Virtex-5 FPGA提供了丰富的I/O资源，手册会指导如何配置和使用这些接口，以适应不同的外部系统连接需求。 5. **嵌入式块RAM与DSP Slice**：V5系列FPGA内含块RAM和专用的数字信号处理（DSP）单元，手册将说明如何有效地利用这些硬件资源实现高效的数据存储和计算。 6. **功耗管理**：手册会介绍如何通过电源管理和功耗优化技术来降低运行功耗，这对于便携式和能源敏感的应用尤为重要。 7. **错误检测与纠正**：FPGA配置过程中可能会出现错误，手册会讲解如何使用内置的错误检测和纠正机制来确保系统的稳定性。 8. **配置选项与安全**：包括加密和安全配置选项，以保护知识产权（IP）不被非法访问。 9. **故障排除**：手册还将提供常见问题的解决策略和故障排除步骤，帮助开发者在遇到问题时快速定位并修复。 10. **支持与更新**：手册最后通常会提供获取技术支持和查找最新更新的途径，以便开发者获取最新的软件工具和设计建议。请注意，尽管Xilinx提供的材料"按原样"提供，不承担任何明示或暗示的保证，但这份用户手册仍然是开发者在使用Virtex-5 FPGA时不可或缺的参考资料。通过深入理解和实践手册中的内容，开发者能够更有效地开发出高性能、可靠的FPGA应用。

16 www.xilinx.com Virtex-5 FPGA Configuration Guide

UG191 (v3.11) October 19, 2012

Chapter 1: Configuration Overview

Configuration constraints can be selected when generating the Virtex-5 bitstream. Certain

configuration operations can be affected by these constraints. For a description of the

available constraints, see the software constraints guide.

Table 1-1: Virtex-5 FPGA Dedicated Configuration Pins

Pin Name Type

(1)

Description

M[2:0] Input Mode pins that determine configuration mode. Sampled on the rising edge of INIT_B.

CCLK Input or

Output

Configuration clock source for all configuration modes except JTAG. Refer to the "Board

Layout for Configuration Clock (CCLK)" section for details.

D_IN Input Serial data input for serial configuration modes.

DOUT_BUSY Output In Serial configuration mode, pin acts as serial data output for daisy-chain

configuration. In SelectMAP mode, pin acts as BUSY output.

DONE Bidirectional,

Open-Drain,

or Active

Active High signal indicating configuration is complete.

0 = FPGA not configured

1 = FPGA configured

Refer to the “BitGen” section of the

Development System Reference Guide for software

settings.

INIT_B Bidirectional,

Input or

Output,

Open-Drain

Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay

configuration. INIT_B is bidirectional during configuration.

After the Mode pins are sampled, INIT_B is an open-drain, active-Low output, indicating

whether a CRC error occurred during configuration or a readback CRC error occurred after

configuration (when enabled):

0 = CRC or IDCODE Error (DONE Low) or Readback CRC Error (DONE High and

Readback CRC enabled)

1 = No CRC error, housecleaning complete.

PROGRAM_B

(2)

Input Active-Low, asynchronous full-chip reset.

HSWAPEN Input Active-High input used to disable weak preconfiguration I/O pull-up resistors:

0 = Weak preconfiguration I/O pull-up resistors enabled

1 = Weak preconfiguration I/O pull-up resistors disabled

HSWAPEN has a weak pull-up prior to and during configuration. HSWAPEN must be

connected to either disable or enable the pull-up resistors. The weak pull-up does not

always provide a reliable 1.

TDI Input Test Data In. This pin is the serial input to all JTAG instruction and data registers. The state

of the TAP controller and the current instruction determine the register that is fed by the

TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic

High to the system if the pin is not driven. TDI is applied into the JTAG registers on the

rising edge of TCK.

TDO Output Test Data Out. This pin is the serial output for all JTAG instruction and data registers. The

state of the TAP controller and the current instruction determine the register (instruction or

data) that feeds TDO for a specific operation. TDO changes state on the falling edge of TCK

and is only active during the shifting of instructions or data through the device. TDO is an

active driver output.

TMS Input Test Mode Select. This pin determines the sequence of states through the TAP controller on

the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the

pin is not driven.

TCK Input Test Clock. This pin is the JTAG Test Clock. TCK sequences the TAP controller and the JTAG

registers in Virtex-5 devices.

Virtex-5 FPGA Configuration Guide www.xilinx.com 17

UG191 (v3.11) October 19, 2012

Configuration Modes and Pins

CS_B Input

Active-Low chip select to enable the SelectMAP data bus (see “SelectMAP Data Loading,”

page 54):

0 = SelectMAP data bus enabled

1 = SelectMAP data bus disabled

RDWR_B Input

Determines the direction of the SelectMAP data bus (see “SelectMAP Data Loading,”

page 54):

0 = inputs (configuration data write)

1 = outputs (configuration data read)

RDWR_B input can only be changed while CS_B is deasserted, otherwise an ABORT occurs

(see

“SelectMAP ABORT,” page 58).

Notes:

1. The Bidirectional type describes a pin that is bidirectional under all conditions. If the pin is an input for some configuration modes or an

output for others, it is listed as an

Input or Output type.

2. Pulsing PROGRAM_B does not reset the JTAG TAP state machine (this behavior differs from Virtex-4 devices).

3. All JTAG and serial dedicated configuration pins are located in a separate, dedicated bank with a dedicated V

CC_CONFIG

supply.

Table 1-1: Virtex-5 FPGA Dedicated Configuration Pins (Continued)

Pin Name Type

(1)

Description

Table 1-2: Virtex-5 FPGA Dual-Purpose Configuration Pins

Pin Name

BPI-Up/

BPI-Down

SelectMAP SPI

I/O

Bank

Description

ADDR[25:20] ADDR[25:20] 2 BPI address bus output.

ADDR[19:0] ADDR[19:0] D[31:16] RCMD

[7:0]

1 BPI address bus output. SelectMAP data I/O for Slave

SelectMAP mode only. SPI read command strapping

inputs RCMD[7:0] (muxed on ADDR[7:0]) when

FS[2:0] = 001. Sampled on rising edge of INIT_B when

used for SPI read command strapping.

RS[1:0]

(1)

RS[1:0] 2 Revision Select outputs.

FCS_B FCS_B FCS_B 2 BPI and SPI Flash chip select output.

FOE_B FOE_B MOSI 2 BPI Flash output enable. SPI data output from FPGA.

FWE_B FWE_B 2 BPI Flash write enable.

CSO_B CSO_B CSO_B 2 Parallel daisy-chain chip select output.

D[7:0] D[7:0] D[7:0] FS[2:0] 2 BPI data input, SelectMAP data in/out. SPI Flash

variant selection. FS[2:0] are on D[2:0].

D[15:8] D[15:8] D[15:8] 4 BPI data input. SelectMAP data in/out.

Notes:

1. RS[1:0] are actively driven to 0 if a configuration error is detected or a watchdog timer event occurs, except in Slave SelectMAP

mode. This can interfere with user logic when used as user I/O. When using the RS[1:0] pins, they should be restricted to be output-

only in User mode.

2. All dual-purpose pins are located in I/O banks with an associated bank supply.

3. If the D0–D7 pins are used as I/O after configuration with at least one of those pins using DCI inputs or outputs, the FreezeDCI

option should not be set to Yes. Otherwise, these I/Os do not function properly. For an output, the I/O is put into a 3-state condition

or does not have the correct termination. For an input, the I/O does not have the correct termination.

18 www.xilinx.com Virtex-5 FPGA Configuration Guide

UG191 (v3.11) October 19, 2012

Chapter 1: Configuration Overview

Configuration Data File Formats

Xilinx design tools can generate configuration data files in a number of different formats,

as described in Table 1-3. BitGen converts the post-PAR NCD file into a configuration file or

a bitstream. PROMGen, the PROM file generator, converts one or more bitstream files into

a PROM file. PROM files can be generated in a number of different file formats and does

not need to be used with a PROM. They can be stored anywhere and delivered by any

means.

Bitstream Overview

The Virtex-5 bitstream contains commands to the FPGA configuration logic as well as

configuration data. Table 1-4 gives a typical bitstream length for each of the Virtex-5

devices.

Table 1-3: Xilinx Configuration File Formats

File

Extension

Bit Swapping

(1)

Xilinx Software

Tool

(2)

Description

BIT

Not

Bit Swapped

BitGen (generated by

default)

Binary configuration data file containing header information

that does not need to be downloaded to the FPGA. Used to

program devices from iMPACT with a programming cable.

RBT

Not

Bit Swapped

BitGen (generated if

-b option is set)

ASCII equivalent of the BIT file containing a text header and

ASCII 1s and 0s. (Eight bits per configuration bit.)

BIN

• BitGen: Not

Bit Swapped

• PROMGen:

Bit Swapped

BitGen (generated if

-g binary:yes

option is set) or

PROMGen

Binary configuration data file with no header information.

Similar to BIT file. Can be used for custom configuration

solutions (for example, microprocessors), or in some cases to

program third-party PROMs.

MCS

EXO

TEK

Bit Swapped

PROMGen or

iMPACT

ASCII PROM file formats containing address and checksum

information in addition to configuration data. Used mainly for

device programmers and iMPACT.

HEX

Determined

by User

PROMGen or

iMPACT

ASCII PROM file format containing only configuration data.

Used mainly in custom configuration solutions.

Notes:

1. Bit swapping is discussed in the “Bit Swapping” section.

2. For complete BitGen and PROMGen syntax, refer to the Development System Reference Guide.

Table 1-4: Virtex-5 FPGA Bitstream Length

Device Total Number of Configuration Bits

(1)

XC5VLX30 8,374,016

XC5VLX50 12,556,672

XC5VLX85 21,845,632

XC5VLX110 29,124,608

XC5VLX155 41,048,064

XC5VLX220 53,139,456

XC5VLX330 79,704,832

20 www.xilinx.com Virtex-5 FPGA Configuration Guide

UG191 (v3.11) October 19, 2012

Chapter 1: Configuration Overview

width. Table 1-5 shows an example bitstream with an inserted bus width detection pattern.

When observing the pattern on the FPGA data pin, the bits are bit swapped, as described

in “Parallel Bus Bit Order.”

The bitstream data in Table 1-5 shows the 32-bit configuration word for an unswapped

bitstream. For a swapped bitstream format, the LSB and MSB order for the individual bytes

are swapped. For example, the Sync word at the FPGA pins in the D[31:00] bit order would

be: 0x5599AA66. For swapped and unswapped formats see “Configuration Data File

Formats.”.

Bus width auto detection is transparent to most users, because all configuration bitstreams

(BIT or RBT files) generated by the Xilinx ISE® Bitstream Generator (BitGen) software

include the Bus Width Auto Detection pattern. These patterns are ignored by the

configuration logic if the Mode pins are set to Master Serial, Slave Serial, JTAG, or SPI

mode.

For the x8 bus, the configuration bus width detection logic first finds 0xBB on the D[0:7]

pins, followed by 0x11. For the x16 bus, the configuration bus width detection logic first

finds 0xBB on D[0:7] followed by 0x22. For the x32 bus, the configuration bus width

detection logic first finds 0xBB, on D[0:7], followed by 0x44.

If the immediate byte after 0xBB is not 0x11, 0x22, or 0x44, the bus width state machine is

reset to search for the next 0xBB until a valid sequence is found. Then it switches to the

appropriate external bus width and starts looking for the Sync word.

Sync Word

A special Sync word is used to allow configuration logic to align at a 32-bit word boundary.

No packet processed by the FPGA until the Sync word is found. The bus width must be

detected successfully for parallel configuration modes before the Sync word can be

detected. Table 1-6 shows the Sync word in an unswapped bitstream format.

Table 1-5: Bus Width Detection Pattern

D[24:31] D[16:23] D[8:15] D[0:7] Comments

0xFF 0xFF 0xFF 0xFF

0x00 0x00 0x00 0xBB Bus Width Pattern

0x11 0x22 0x00 0x44 Bus Width Pattern

0xFF 0xFF 0xFF 0xFF

0xAA 0x99 0x55 0x66 Sync Word

……………

Table 1-6: Sync Word

31:24 23:16 15:8 7:0

0xAA 0x99 0x55 0x66

剩余165页未读，继续阅读

wangwei19880311

粉丝: 0
资源: 1

赛灵思V5 FPGA配置指南

Virtex-5 FPGA用户手册：设计与应用指南

Virtex-5 FPGA用户手册：中文版，详解架构与功能

AG16K FPGA用户手册使用指南

FPGA使用手册

MYiR Zynq FPGA使用手册

小梅哥FPGA使用手册

AGM FPGA替代ALTERA FPGA使用手册.pdf

FPGA使用手册 - 附件2

FPGA使用手册 - 附件1

Xilinx7系列FPGA用户手册

最新资源