PCI Express 4.0 规范详解：新一代高速接口标准

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"PCI_Express 4.0 规范是官方发布的关于PCI Express技术的最新版本，旨在提供更高的数据传输速率和更先进的功能。该规范涵盖了带宽、错误处理、电源管理等多个方面，适用于超高清设备和其他高性能计算需求。" PCI Express（Peripheral Component Interconnect Express），简称PCIe，是一种高速接口标准，用于计算机系统中的外部设备间的数据交换，如显卡、网卡、硬盘等。PCIe 4.0规范是这一接口技术的第四代更新，显著提升了数据传输速率。 PCIe 4.0规范的主要改进包括： 1. **数据速率翻倍**：相比PCIe 3.0的8 GT/s（吉比特每秒），PCIe 4.0将数据传输速率提升至16 GT/s，这意味着每个通道的双向带宽达到32 Gbps（吉比特每秒）。双通道（x2）配置可以提供64 Gbps，四通道（x4）配置则可提供128 Gbps，依此类推，对于高带宽需求的设备如SSD固态硬盘和高分辨率显卡，提供了更大的性能潜力。 2. **信号完整性优化**：随着速度的提高，信号完整性成为一大挑战。PCIe 4.0引入了新的信号编码方案，如前向纠错（FEC，Forward Error Correction）和更先进的信号调理技术，以确保在高速下保持低误码率。 3. **电源效率与管理**：规范中包含了动态电源分配（Dynamic Power Allocation ECN）和增强的电源管理特性，允许设备根据实际工作负载调整功耗，从而降低整体系统能耗。 4. **错误处理与报告**：增加了内部错误报告机制，提高了系统的可靠性和稳定性，通过内部Error Reporting ECN，系统能更好地检测并处理潜在的硬件问题。 5. **多播支持**：Multicast ECN使得数据能够在多个接收者之间高效分发，这对于数据中心和服务器环境中的并行处理非常有用。 6. **原子操作**：Atomic Operations ECN提供了新的原子操作支持，增强了设备间的同步和一致性，这对于实时操作和多处理器通信至关重要。 7. **可扩展性**：Resizable BAR Capability ECN允许系统更灵活地分配内存资源，使设备能更有效地利用系统内存。 8. **ID-Based Ordering ECN** 和 **Latency Tolerance Reporting ECN** 提供了更精细的事务排序和延迟容忍度管理，有助于优化系统性能和响应时间。 9. **Alternative Routing-ID Interpretation (ARI)**：ARI ECN改进了地址解析，使得设备可以在复杂的多层级配置中更高效地通信。 10. **增强的标签功能**：Extended Tag Enable Default功能可能允许系统处理更多的并发事务，提高并行处理能力。 PCIe 4.0规范是为满足当前和未来高性能设备的需求而设计的，它的高带宽、低延迟和增强的特性为超高清视频处理、游戏、大数据分析和人工智能应用等提供了强大的基础。

PCI Express Base Specification, Rev. 4.0 Version 1.0

10.3.5 Invalidate Flow Control .................................................................................... 1191

10.3.6 Invalidate Ordering Semantics ......................................................................... 1192

10.3.7 Implicit Invalidation Events .............................................................................. 1193

10.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1194

10.4 PAGE REQUEST SERVICES .......................................................................................... 1195

10.4.1 Page Request Message ...................................................................................... 1196

10.4.2 Page Request Group Response Message .......................................................... 1200

10.5 CONFIGURATION ........................................................................................................ 1202

10.5.1 ATS Extended Capability Structure .................................................................. 1202

10.5.2 Page Request Extended Capability Structure ................................................... 1205

A. ISOCHRONOUS APPLICATIONS ................................................................................. 1212

A.1. INTRODUCTION .......................................................................................................... 1212

A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1214

A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1215

A.2.2. Isochronous Payload Size ................................................................................. 1216

A.2.3. Isochronous Bandwidth Allocation ................................................................... 1216

A.2.4. Isochronous Transaction Latency ..................................................................... 1217

A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1218

A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1219

A.4. TRANSACTION ORDERING .......................................................................................... 1219

A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1219

A.6. FLOW CONTROL ......................................................................................................... 1220

A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1220

A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1220

A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1220

A.7.3. Isochronous Bandwidth of Switches ................................................................. 1220

A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1221

A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1221

A.8.1. An Endpoint as a Requester .............................................................................. 1221

A.8.2. An Endpoint as a Completer ............................................................................. 1221

A.8.3. Switches............................................................................................................. 1222

A.8.4. Root Complex .................................................................................................... 1223

B. SYMBOL ENCODING .................................................................................................... 1224

C. PHYSICAL LAYER APPENDIX .................................................................................... 1233

C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1233

C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................. 1239

D. REQUEST DEPENDENCIES .......................................................................................... 1242

E. ID-BASED ORDERING USAGE .................................................................................... 1245

E.1. INTRODUCTION .......................................................................................................... 1245

E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1246

E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1246

E.2.2. Benefits for Switched Environments ................................................................. 1246

E.2.3. Benefits for Integrated Endpoints ..................................................................... 1247

PCI Express Base Specification, Rev. 4.0 Version 1.0

E.2.4. IDO Use in Conjunction with RO ..................................................................... 1247

E.3. WHEN TO USE IDO .................................................................................................... 1247

E.4. WHEN NOT TO USE IDO ............................................................................................ 1248

E.4.1. When Not to Use IDO with Endpoints .............................................................. 1248

E.4.2. When Not to Use IDO with Root Ports ............................................................. 1248

E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1249

E.5.1. Software Control of Endpoint IDO Use ............................................................ 1249

E.5.2. Software Control of Root Port IDO Use ........................................................... 1250

F. MESSAGE CODE USAGE .............................................................................................. 1251

G. PROTOCOL MULTIPLEXING ................................................................................... 1253

G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1256

G.2. PMUX PACKETS ........................................................................................................ 1261

G.3. PMUX PACKET LAYOUT ........................................................................................... 1262

G.3.1. PMUX Packet Layout for 8b/10b Encoding ..................................................... 1262

G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1264

G.4. PMUX CONTROL ....................................................................................................... 1267

G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1267

G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1268

G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1269

G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1270

G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1272

G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) .......................................... 1275

H. FLOW CONTROL UPDATE LATENCY AND ACK UPDATE LATENCY

CALCULATIONS .................................................................................................................... 1277

H.1. FLOW CONTROL UPDATE LATENCY ........................................................................... 1277

H.2. ACK LATENCY ........................................................................................................... 1279

ACKNOWLEDGEMENTS ...................................................................................................... 1282

PCI Express Base Specification, Rev. 4.0 Version 1.0

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 56

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 57

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 61

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 63

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 64

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 69

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 72

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 73

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 74

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 75

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 80

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 82

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 82

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 84

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 84

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 85

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 88

FIGURE 2-13: TRANSACTION ID .................................................................................................... 88

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 95

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 98

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 98

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 99

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ...................... 100

FIGURE 2-19: TPH TLP PREFIX .................................................................................................. 101

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ........................................... 101

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ........................................... 102

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ....................... 102

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ... 103

FIGURE 2-24: MESSAGE REQUEST HEADER ................................................................................ 105

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 114

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 116

FIGURE 2-27: LN MESSAGE ......................................................................................................... 117

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 118

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 120

FIGURE 2-30: HIERARCHY ID MESSAGE ..................................................................................... 121

FIGURE 2-31: LTR MESSAGE ...................................................................................................... 123

FIGURE 2-32: OBFF MESSAGE ................................................................................................... 123

FIGURE 2-33: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 124

FIGURE 2-34: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 125

FIGURE 2-35: COMPLETION HEADER FORMAT ............................................................................ 126

FIGURE 2-36: (NON-ARI) COMPLETER ID .................................................................................. 126

FIGURE 2-37: ARI COMPLETER ID .............................................................................................. 127

FIGURE 2-38: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 133

FIGURE 2-39: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 135

PCI Express Base Specification, Rev. 4.0 Version 1.0

FIGURE 2-40: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 140

FIGURE 2-41: EXAMPLE COMPLETION DATA WHEN SOME BYTE ENABLES ARE 0B ..................... 144

FIGURE 2-42: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 156

FIGURE 2-43: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 157

FIGURE 2-44: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 159

FIGURE 2-45: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 160

FIGURE 2-46: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION ........................................................................................................................ 177

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 185

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 188

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED

FRAMING ............................................................................................................................. 196

FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 198

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 201

FIGURE 3-6: NOP DATA LINK LAYER PACKET FORMAT ............................................................. 201

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 201

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 201

FIGURE 3-9: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 202

FIGURE 3-10: PM DATA LINK LAYER PACKET FORMAT ............................................................. 202

FIGURE 3-11: VENDOR-SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 202

FIGURE 3-12: DATA LINK FEATURE DLLP ................................................................................. 202

FIGURE 3-13: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 204

FIGURE 3-14: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 204

FIGURE 3-15: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS

............................................................................................................................................. 207

FIGURE 3-16: CALCULATION OF LCRC ...................................................................................... 209

FIGURE 3-17: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 215

FIGURE 3-18: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 216

FIGURE 3-19: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 220

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 225

FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 226

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 227

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 227

FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 230

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 231

FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 231

FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 232

FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 232

FIGURE 4-10: LFSR WITH 8B/10B SCRAMBLING POLYNOMIAL ................................................... 234

FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A

BLOCK ................................................................................................................................. 235

FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 236

FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 239

FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 241

FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 241

FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 242

PCI Express Base Specification, Rev. 4.0 Version 1.0

FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 242

FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 250

FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 252

FIGURE 4-20: 8.0 GT/S EQUALIZATION FLOW ............................................................................. 260

FIGURE 4-21: 16.0 GT/S EQUALIZATION FLOW ........................................................................... 261

FIGURE 4-22: ELECTRICAL IDLE EXIT ORDERED SET FOR 8.0 GT/S AND ABOVE DATA RATES ... 273

FIGURE 4-23: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 288

FIGURE 4-24: DETECT SUBSTATE MACHINE ............................................................................... 290

FIGURE 4-25: POLLING SUBSTATE MACHINE .............................................................................. 301

FIGURE 4-26: CONFIGURATION SUBSTATE MACHINE .................................................................. 317

FIGURE 4-27: RECOVERY SUBSTATE MACHINE ........................................................................... 344

FIGURE 4-28: L0S SUBSTATE MACHINE ...................................................................................... 350

FIGURE 4-29: L1 SUBSTATE MACHINE ........................................................................................ 352

FIGURE 4-30: L2 SUBSTATE MACHINE ........................................................................................ 354

FIGURE 4-31: LOOPBACK SUBSTATE MACHINE ........................................................................... 359

FIGURE 4-32: RECEIVER NUMBER ASSIGNMENT ......................................................................... 376

FIGURE 4-33: SUPPORTED TOPOLOGIES ................................................................................. 390

FIGURE 4-34: RETIMER CLKREQ# CONNECTION TOPOLOGY .................................................... 420

FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 428

FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 437

FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT ........................ 440

FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING . 443

FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE .................................................. 447

FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED) ................ 460

FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 461

FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 463

FIGURE 5-9: STATE DIAGRAM FOR L1 PM SUBSTATES ................................................................ 468

FIGURE 5-10: DOWNSTREAM PORT WITH A SINGLE PLL ............................................................. 469

FIGURE 5-11: MULTIPLE DOWNSTREAM PORTS WITH A SHARED PLL ......................................... 470

FIGURE 5-12: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 472

FIGURE 5-13: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 473

FIGURE 5-14: L1.2 SUBSTATES .................................................................................................... 474

FIGURE 5-15: EXAMPLE: ILLUSTRATION OF BOUNDARY CONDITION DUE TO DIFFERENT SAMPLING

CLKREQ# ...................................................................................................................... 475

FIGURE 5-16: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 477

FIGURE 5-17: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 477

FIGURE 5-18: FUNCTION POWER MANAGEMENT STATE TRANSITIONS ....................................... 480

FIGURE 5-19: NON-BRIDGE FUNCTION POWER MANAGEMENT DIAGRAM .................................. 481

FIGURE 5-20: PCI EXPRESS BRIDGE POWER MANAGEMENT DIAGRAM ...................................... 486

FIGURE 6-1: ERROR CLASSIFICATION .......................................................................................... 501

FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING

OPERATIONS ........................................................................................................................ 518

FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 519

FIGURE 6-4: TC FILTERING EXAMPLE ......................................................................................... 538

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