Xilinx UltraScale DSP架构与48E2 Slice详解

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"《Xilinx UltraScale架构与DSP48E2片上DSP用户指南》(UG579 v1.5，发布日期：2017年10月18日)详细介绍了Xilinx公司最新的UltraScale架构下的数字信号处理器(DSP)特性。该文档涵盖了UltraScale DSP Slice的设计、功能和使用方法，旨在帮助工程师深入理解并充分利用这些高性能计算单元。首先，UltraScale Architecture部分概述了这款新型架构的核心优势，包括更高效的处理能力、增强的并行处理能力和更低的功耗。DSP48E2 Slice作为核心组件，是基于UltraScale架构的专门设计，每个Slice通常包含48个独立的运算单元，用于执行乘法和加法运算。文档详细地讲解了DSP Slice的内部结构，如Pattern Detector、X-multiplexers、P/C-multiplexers等部件的功能和工作原理。例如，P/C-multiplexer是一个选择器，用于在不同的数据路径之间切换，提高数据处理的灵活性。而在时钟区域的级联使用也被提及，这对于处理时序同步问题至关重要。在性能比较部分，文档更新了与前一代产品的差异，如表1-2中展示了不同版本DSP的性能指标变化。特别提到了KU3P和KU7P的调整，以及对预加法器（pre-adder）这类嵌入式功能的强化。表2-1和表2-2列出了DSP Slice的运算单元配置，包括预加法器、乘法器A和B端口，以及它们在数据处理流程中的作用。此外，文档还强调了嵌入式功能，如在第34页提到的预加法器作为一项内建功能，可以加速运算过程。最后，文档提供的用户指南提供了操作步骤和注意事项，包括如何正确连接和配置DSP Slice，以及如何通过编程接口实现高效的算法实现。随着文档的修订历史，可以确保读者获得的是最新且最准确的信息，有助于优化设计流程并提升整体系统性能。《ug579-ultrascale-dsp.pdf》是一份实用的参考资源，对于Xilinx UltraScale DSP的使用者来说，无论是进行新项目的设计还是优化现有系统，都能从中获取到宝贵的知识和指导。"

UltraScale Architecture DSP48E2 Slice 13

UG579 (v1.5) October 18, 2017 www.xilinx.com

Chapter 2: DSP48E2 Functionality

The DSP48E2 supports many independent functions. These functions include:

•Multiply

• Multiply accumulate (MACC)

•Multiply add

•Four-input add

• Barrel shift

• Wide-bus multiplexing

• Magnitude comparator

• Bitwise logic functions

•Wide XOR

• Pattern detect

• Wide counter

The architecture also supports cascading multiple DSP48E2 slices to form wide math

functions, DSP filters, and complex arithmetic without the use of general logic.

DSP48E2 Features

The features in the DSP48E2 slice are:

• 27-bit pre-adder with D register to enhance the capabilities of the A or B path

• A or B can be selected as pre-adder input to allow for wider multiplication coefficients

• The result of the pre-adder can be sent to both inputs of the multiplier to provide

squaring capability

• INMODE control supports balanced pipelining when dynamically switching between

multiply (A*B) and add operations (A+B)

• 27 x 18 multiplier

• 30-bit A input of which the lower 27 bits feed the A input of the multiplier, and the

entire 30-bit input forms the upper 30 bits of the 48-bit A:B concatenated internal bus

• Cascading A and B input:

Semi-independently selectable pipelining between direct and cascade paths

Separate clock enables for two-deep A and B set of input registers

• Independent C input and C register with independent reset and clock enable

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UltraScale Architecture DSP48E2 Slice 15

UG579 (v1.5) October 18, 2017 www.xilinx.com

Chapter 2: DSP48E2 Functionality

Support for wider add/subtracts

Available for each SIMD adder (up to four)

Cascaded CARRYCASCOUT and MULTSIGNOUT allows for MACC extensions up to

96 bits

• Single clock for synchronous operation

• Optional input, pipeline, and output/accumulate registers

• Optional registers for control signals (OPMODE, ALUMODE, and CARRYINSEL)

• Independent clock enable and synchronous resets with programmable polarity for

greater flexibility

• Internal multiplier and XOR logic can be gated off when unused to save power

The DSP slice consists of a multiplier followed by an accumulator. At least three pipeline

registers are required for both multiply and multiply-accumulate operations to run at full

speed. The multiply operation in the first stage generates two partial products that need to

be added together in the second stage.

When only one or two registers exist in the multiplier design, the M register should always

be used to save power and improve performance.

Add/Sub and Logic Unit operations require at least two pipeline registers (input, output) to

run at full speed.

The cascade capabilities of the DSP slice are extremely efficient at implementing

high-speed pipelined filters built on the adder cascades instead of adder trees.

Multiplexers are controlled with dynamic control signals, such as OPMODE, ALUMODE, and

CARRYINSEL, enabling a great deal of flexibility. Designs using registers and dynamic

opmodes are better equipped to take advantage of the DSP slice’s capabilities than

combinatorial multiplies.

In general, the DSP slice supports both sequential and cascaded operations due to the

dynamic OPMODE and cascade capabilities. Fast Fourier Transforms (FFTs), floating point,

computation (multiply, add/sub, divide), counters, and large bus multiplexers are some

applications of the DSP slice.

Additional capabilities of the DSP slice include synchronous resets and clock enables, dual

A input pipeline registers, pattern detection, Logic Unit functionality, single

instruction/multiple data (SIMD) functionality, and MACC and Add-Acc extension to 96 bits.

The DSP slice supports convergent and symmetric rounding, terminal count detection and

auto-resetting for counters, and overflow/underflow detection for sequential accumulators.

A 96-bit wide XOR function can be implemented as eight 12-bit wide XOR, four 24-bit wide

XOR, or two 48-bit wide XOR.

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