SATA3.0规范详解：硬件、Link层与传输层定义

sata3.0规范

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"sata3.0规范" Serial ATA（SATA）是一种高速串行接口标准，用于连接计算机系统中的存储设备，如硬盘驱动器和光驱。SATA 3.0是该规范的一个重要版本，它在2009年发布，由包括Dell、Hewlett-Packard、Hitachi、Intel、Maxim Integrated Products、Seagate Technology和Western Digital等在内的SATA-IO（Serial ATA International Organization）成员共同制定。SATA 3.0规范的目标是提高数据传输速度和整体性能，以满足不断增长的存储需求。在SATA 3.0规范中，主要的改进和特点包括： 1. **传输速率提升**：SATA 3.0的最大数据传输速率达到了6Gbps（600MB/s），这是相对于前一代SATA 2.0（3Gbps）的两倍。尽管实际的持续传输速率可能会因为各种因素而降低，但理论上的最大带宽增加显著提升了数据传输的速度。 2. **NCQ（Native Command Queuing）优化**：NCQ是一种优化硬盘读写命令顺序的技术，有助于减少磁头移动，从而提高效率和性能。在SATA 3.0中，NCQ的深度进一步提升，允许更高效的数据处理。 3. **Power Management增强**：规范支持更先进的电源管理功能，如节能模式（Slumber mode），可以降低设备在空闲状态下的功耗，从而提高了能效。 4. **Port Multiplier和Port Selectors的改进**：这些组件允许一个SATA接口控制多个设备，SATA 3.0对它们的兼容性和性能进行了优化，使得多设备连接更加稳定。 5. **Hot-plugging支持**：即热插拔功能，用户可以在不关闭系统的情况下添加或移除SATA设备，增强了系统的灵活性和可用性。 6. **TRIM指令**：对于固态硬盘（SSD）来说，TRIM是一个重要的特性，它允许操作系统通知SSD哪些数据块已经不再使用，以便于SSD进行垃圾回收，从而保持最佳性能。 7. **改进的错误检测与恢复机制**：SATA 3.0规范增强了错误检测和纠正能力，确保了数据传输的可靠性。 8. **端到端数据保护**：通过CRC（Cyclic Redundancy Check）等技术，SATA 3.0提供了一种端到端的数据完整性检查，确保数据在传输过程中不被损坏。 9. **兼容性**：SATA 3.0规范设计时考虑了向后兼容性，这意味着新的SATA 3.0设备可以无缝地工作在旧的SATA 2.0或更低版本的接口上，虽然速度可能受到限制。 SATA 3.0规范通过一系列技术和功能的更新，极大地提升了存储设备的性能和系统的灵活性，同时也为固态硬盘的普及提供了坚实的基础。这一规范不仅推动了硬件技术的发展，也为用户提供了更快的数据访问速度和更稳定的存储体验。

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Serial ATA Revision 3.0 Gold Revision page 16 of 663

Figure 161 – Receiver Jitter and CM Tolerance Test – Setting TJ and CM Levels (Gen3i) ....... 294

Figure 162 – Receiver Jitter and CM Tolerance Test (Gen3i) .................................................... 294

Figure 163 – Return Loss Test-Calibration ................................................................................. 295

Figure 164 – Return Loss Test .................................................................................................... 297

Figure 165 – Intra-Pair Skew Test for a Transmitter ................................................................... 299

Figure 166 – Receiver Intra-Pair Skew Test—Setting Levels ..................................................... 299

Figure 167 – Receiver Intra-Pair Skew Test ............................................................................... 299

Figure 168 – Example Intra-Pair Skew test for Transmitter (10.8 pS) ........................................ 300

Figure 169 – TX/RX Sequencing Transient Voltage Measurement ............................................ 300

Figure 170 – AC Coupled Capacitance Measurement................................................................ 301

Figure 171 – Squelch Detector Threshold Test—Setting Levels ................................................ 303

Figure 172 – Squelch Detector Threshold Test........................................................................... 304

Figure 173 – TDR Differential Impedance Test—Setting Risetime............................................. 306

Figure 174 – TDR Impedance Test ............................................................................................. 306

Figure 175 – TDR Single-Ended Impedance Test—Setting Risetime ........................................ 307

Figure 176 – DC Coupled Common Mode Voltage Measurement.............................................. 307

Figure 177 – AC Coupled Common Mode Voltage Measurement.............................................. 308

Figure 178 – TDR Impedance Test ............................................................................................. 308

Figure 179 - Sequencing Transient Voltage Laboratory Load .................................................... 309

Figure 180 – OOB Signals........................................................................................................... 310

Figure 181 – Transmitter Examples ............................................................................................ 311

Figure 182 – Transmitter Examples (Concluded)........................................................................ 312

Figure 183 – COMRESET Sequence.......................................................................................... 313

Figure 184 – COMINIT Sequence ............................................................................................... 314

Figure 185 – OOB Signal Detector.............................................................................................. 316

Figure 186 – Squelch Detector.................................................................................................... 317

Figure 187 – Power-On Sequence.............................................................................................. 330

Figure 188 – PHYRDY to Partial—Host Initiated ........................................................................ 332

Figure 189 – PHYRDY to Partial—Device Initiated..................................................................... 333

Figure 190 – Nomenclature Reference ....................................................................................... 336

Figure 191 – Bit Ordering and Significance................................................................................. 346

Figure 192 – Transmission Structures ........................................................................................ 348

Figure 193 – FIS type value assignments ................................................................................... 383

Figure 194 – Register - Host to Device FIS layout ...................................................................... 384

Figure 195 – Register - Device to Host FIS layout ...................................................................... 386

Figure 196 – Set Device Bits - Device to Host FIS layout ........................................................... 387

Figure 197 – DMA Activate - Device to Host FIS layout.............................................................. 388

Figure 198 – DMA Setup – Device to Host or Host to Device FIS layout ................................... 389

Figure 199 – BIST Activate - Bidirectional................................................................................... 392

Figure 200 – PIO Setup - Device to Host FIS layout................................................................... 395

Figure 201 – Data – Host to Device or Device to Host FIS layout .............................................. 397

Figure 202 –DEVICE CONFIGURATION IDENTIFY data structure ........................................... 494

Figure 203 - DEVICE CONFIGURATION SET data structure .................................................... 495

Figure 204 – DMA Setup FIS definition for memory buffer selection .......................................... 501

Figure 205 – READ FPDMA QUEUED command definition....................................................... 504

Figure 206 – READ FPDMA QUEUED error on command receipt............................................. 506

Figure 207 - Set Device Bits FIS with error notification, and command completions ................. 507

Figure 208 - Set Device Bits FIS aborting all outstanding command.......................................... 508

Figure 209 – WRITE FPDMA QUEUED command definition ..................................................... 509

Figure 210 - Set Device Bits FIS for successful WRITE FPDMA QUEUED command completion

............................................................................................................................................. 510

Figure 211 – WRITE FPDMA QUEUED error on command receipt ........................................... 511

Figure 212 - Set Device Bits FIS with error notification, and command completions ................. 512

Figure 213 - NCQ QUEUE MANAGEMENT - Command definition ........................................... 513

Figure 214 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - Successful completion........ 515

Figure 215 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - error on command receipt .. 516

Serial ATA Revision 3.0 Gold Revision page 17 of 663

Figure 216 - NCQ QUEUE MANAGEMENT, Abort NCQ Queue – error during execution......... 517

Figure 217 – NCQ QUEUE MANAGEMENT, Deadline Handling - Successful completion........ 520

Figure 218 – NCQ QUEUE MANAGEMENT, Deadline Handling - error on command receipt .. 520

Figure 219 - NCQ QUEUE MANAGEMENT, Deadline Handling – error during execution......... 521

Figure 220 – Example DMA engine indirection for First-party DMA support .............................. 522

Figure 221 – Queued Error Log data structure definition ............................................................ 525

Figure 222 – NCQ Queue Management Log (12h) data structure definition .............................. 527

Figure 223 – Phy Event Counter Identifiers ................................................................................ 530

Figure 224 – Phy Event Counters Log data structure definition.................................................. 532

Figure 225 – Generic enclosure services topology ..................................................................... 537

Figure 226 – Simplified view of generic topology ........................................................................ 537

Figure 227 – Enclosure services definition configuration ............................................................ 538

Figure 228 – Register Signature Indicating Presence of Enclosure Services Device................. 539

Figure 229 – Register Signature for Absent Enclosure Processor.............................................. 539

Figure 230 – Command Block Register Fields Used in Enclosure Processor Communications 540

Figure 231 – I

C Frame for Conveying an Enclosure Services Command ................................. 541

Figure 232 – WRITE SEP Command Block Registers................................................................ 542

Figure 233 – I

C Transactions Corresponding to a WRITE SEP Command .............................. 543

Figure 234 – READ SEP Command Block Registers ................................................................. 544

Figure 235 – I

C Transactions Corresponding to READ SEP Command ................................... 544

Figure 236 – IDENTIFY SEP data structure definition ................................................................ 545

Figure 237 – SAF-TE Write Device Slot Status data structure ................................................... 547

Figure 238 – SES Device Element data structure....................................................................... 548

Figure 239 – Example Subsystem............................................................................................... 549

Figure 240 – SAF-TE Device ID field convention........................................................................ 549

Figure 241 – SES Slot Address field convention......................................................................... 550

Figure 242 – Activity LED definition for desktop behavior emulation.......................................... 552

Figure 243 – Device Activity LEDs with Separate Wires............................................................. 553

Figure 244 – Device Activity LEDs with Ribbon Cable................................................................ 554

Figure 245 – Device Activity LEDs in a Storage Subsystem....................................................... 555

Figure 246 – Software reset to control port result values............................................................ 556

Figure 247 – Port Multiplier Signature......................................................................................... 558

Figure 248 – SActive register definition....................................................................................... 565

Figure 249 – SNotification register definition............................................................................... 565

Figure 250 – Error handling architecture..................................................................................... 567

Figure 251 – Port Multiplier Overview ......................................................................................... 577

Figure 252 – Port Selector Overview........................................................................................... 607

Figure 253 – Example Failover Application with Two Hosts ....................................................... 608

Figure 254 – Port selection signal based on assertion of COMRESET to assertion of following

COMRESET ........................................................................................................................ 610

Figure 255 – Complete port selection signal consisting of two sequences with requisite inter-reset

spacings............................................................................................................................... 611

Figure 256 – Control State Machine............................................................................................ 613

Figure 257 – Phy Block Diagram................................................................................................. 614

Figure 258 – Concept summary interconnect structure .............................................................. 644

Figure 259 – An example of signal connections with one I/O Controller..................................... 645

Figure 260 – Example of signal connections with two I/O Modules ............................................ 647

Figure 261 – High Speed Channels – Configuration 0................................................................ 648

Figure 262 – High-Speed Channels – Configuration 1 ............................................................... 648

Figure 263 – Low Speed Channels ............................................................................................. 649

Figure 264 – Interconnect Channels ........................................................................................... 649

Figure 265 – I/O Controller Module Connector Rendering.......................................................... 650

Figure 266 – Connector Pin Layout and Pin Lengths.................................................................. 651

Figure 267 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 652

Figure 268 – Side View of Connector.......................................................................................... 652

Figure 269 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 654

Serial ATA Revision 3.0 Gold Revision page 19 of 663

LIST OF TABLES

Table 1 – State Table Cell Description.......................................................................................... 44

able 2 – Usage Model Descriptions............................................................................................. 50

Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 82

Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 91

Table 5 – Housing and contact electrical parameters, test procedures, and requirements.......... 95

Table 6 – Mechanical test procedures and requirements ............................................................. 96

Table 7 – Environmental parameters, test procedures, and requirements ................................... 97

Table 8 – Additional requirement................................................................................................... 97

Table 9 – Connector test sequences............................................................................................. 98

Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence............. 119

Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 119

Table 12 – Slimline Connector Location References .................................................................. 122

Table 13 – Slimline Device plug connector pin definition ............................................................ 131

Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 138

Table 15 - Signal and Power Internal LIF-SATA Plug ................................................................. 145

Table 16 - Unique Connector Mechanical Testing Procedures and Requirements .................... 146

Table 17 – Multilane Pin Assignments ........................................................................................ 161

Table 18 – Internal Cable / Connector Measurement Parameter and Requirements................. 165

Table 19 – External Single Lane Cable / Connector Measurement Parameter and Requirements

............................................................................................................................................. 165

Table 20 – Limited External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 166

Table 21 – Extended External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 166

Table 22 – Common Interconnect Measurement Procedure Methodologies.............................. 169

Table 23 – Interconnect Test Methodologies / Procedures......................................................... 170

Table 24 – Power segment pin P11 activity signal electrical parameters ................................... 176

Table 25 – Host activity signal electrical parameters .................................................................. 176

Table 26 – Activity signal functional states.................................................................................. 177

Table 27 – Host staggered spin-up control electrical requirements ............................................ 178

Table 28 – Comparator voltages for alternate example presence detection circuit .................... 181

Table 29 – General Specifications............................................................................................... 193

Table 30 – Transmitter Specifications ......................................................................................... 195

Table 31 – Transmitted Signal Requirements ............................................................................. 198

Table 32 – Receiver Specifications ............................................................................................. 202

Table 33 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 206

Table 34 – OOB Specifications ................................................................................................... 209

Table 35 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 233

Table 36 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 234

Table 37 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 235

Table 38 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 236

Table 39 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 237

Table 40 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+ ..................... 238

Table 41 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 239

Table 42 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 239

Table 43 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 240

Table 44 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 240

Table 45 – Composite-Bit Pattern (COMP) Starting with RD–.................................................... 241

Table 46 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 244

Table 47 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 262

Table 48 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 264

Table 49 – OOB Signal Times..................................................................................................... 310

Table 50 – Interface Power States .............................................................................................. 319

Serial ATA Revision 3.0 Gold Revision page 20 of 663

Table 51 – State Diagram Host Phy Initialization State Machine................................................ 321

Table 52 – State Diagram Device Phy Initialization State Machine ............................................ 325

Table 53 – Bit Designations......................................................................................................... 336

Table 54 – Conversion Examples................................................................................................ 337

Table 55 – 5B/6B Coding ............................................................................................................ 339

Table 56 – 3B/4B Coding ............................................................................................................ 339

Table 57 – Encoding Examples................................................................................................... 340

Table 58 – Valid Data Characters ............................................................................................... 341

Table 59 – Valid Control Characters ........................................................................................... 345

Table 60 – Single Bit Error with Two Character Delay ................................................................ 347

Table 61 – Single Bit Error with One Character Delay ................................................................ 347

Table 62 – Description of Primitives............................................................................................ 349

Table 63 – Primitive Encoding..................................................................................................... 350

Table 64 – CONT

Usage Example ............................................................................................ 352

Table 65 – Example of Components of a Round Trip Delay....................................................... 355

Table 66 – SRST Write from Host to Device Transmission Breaking Through a Device to Host

Data FIS............................................................................................................................... 356

Table 67 – Command Shadow Register Block Register Transmission Example ....................... 356

Table 68 – Data from Host to Device Transmission Example..................................................... 357

Table 69 – State Diagram Link Idle ............................................................................................. 360

Table 70 – State Diagram Link Transmit..................................................................................... 363

Table 71 – State Diagram Link Receive...................................................................................... 370

Table 72 – State Diagram Link Power Mode............................................................................... 376

Table 73 – Simplified Shadow Register Block register numbering ............................................. 382

Table 74 – BIST Activate FIS Modes and Bit Settings ................................................................ 393

Table 75 – IDENTIFY DEVICE information................................................................................. 479

Table 76 - Coded Values for Negotiated Serial ATA Signaling Speed ....................................... 484

Table 77 – IDENTIFY PACKET DEVICE information ................................................................. 487

Table 78 - Features enable/disable values ................................................................................. 492

Table 79 - Feature identification values ...................................................................................... 492

Table 80 - Subcommand Field .................................................................................................... 513

Table 81 - Abort Type.................................................................................................................. 515

Table 82- Log Addresses for Serial ATA..................................................................................... 523

Table 83 - General Purpose Log directory values for Serial ATA ............................................... 524

Table 84 – SCR definition............................................................................................................ 560

Table 85 – SCR Definition ........................................................................................................... 560

Table 86 – State Diagram Collisions ........................................................................................... 581

Table 87 – State Diagram Hot Plug State Machine for Host Port ............................................... 583

Table 88 – State Diagram Hot Plug State Machine for Device Port............................................ 585

Table 89 – Register Values for an Unsupported Command ....................................................... 588

Table 90 – Static Information Registers ...................................................................................... 590

Table 91 – Status Information and Control Registers ................................................................. 592

Table 92 – Features Supported Registers .................................................................................. 596

Table 93 – Features Enabled Registers ...................................................................................... 597

Table 94 – Vendor Unique Registers .......................................................................................... 598

Table 95 – Phy Event Counter Registers .................................................................................... 599

Table 96 – Reserved Registers ................................................................................................... 599

Table 97 – PSCR Definition......................................................................................................... 600

Table 98 – READ PORT MULTIPLIER Command Definition ..................................................... 600

Table 99 – READ PORT MULTIPLIER Success Status Result Values ...................................... 601

Table 100 – READ PORT MULTIPLIER Error Status Result Values.......................................... 602

Table 101 – WRITE PORT MULTIPLIER Command Definition.................................................. 602

Table 102 – WRITE PORT MULTIPLIER Success Status Result Values .................................. 603

Table 103 – WRITE PORT MULTIPLIER Error Status Result Values ........................................ 604

Table 104 – Port selection signal inter-reset timing requirements .............................................. 610

Table 105 – CRC and scrambler calculation example - PIO Write Command ........................... 630

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